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ICS831724I датащи(PDF) 18 Page - Integrated Device Technology

номер детали ICS831724I
подробное описание детали  LVCMOS interface levels for all control inputs
PDF  24 Pages
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производитель  IDT [Integrated Device Technology]
домашняя страница  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS831724I датащи(HTML) 18 Page - Integrated Device Technology

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ICS831724AKI REVISION A MAY 16, 2013
18
©2013 Integrated Device Technology, Inc
ICS831724I Data Sheet
DIFFERENTIAL CLOCK DATA MULTIPLEXER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS831724I.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS831724I is the sum of the core power plus the power dissipated at the output(s).
The following is the power dissipation for VDD = 3.3V ± 0.3V = 3.6V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated at the output(s).
Total PowerMAX =VDD_MAX *(IDD_MAX) = 3.6V * 128mA = 460.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 37.0°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.4608W *37.0°C/W = 102.05°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
JA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
32.4°C/W
29.0°C/W



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