Low-Power, 622Mbps Limiting Amplifiers

with Chatter-Free Power Detect for LANs

6

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_______________Detailed Description

Figure 1 shows the functional diagram for the MAX3761/

MAX3762. The input signal is applied to VIN+ and VIN-.

A chain of amplifier stages, each contributing approxi-

mately 12.5dB of gain, amplifies the input signal to

PECL output voltage swings. A 4mVp-p input signal will

cause the output to fully limit.

Received-Signal-Strength

Indicator (RSSI)

Each amplifier stage contains a full-wave logarithmic

detector (FWD). The full-wave detector outputs are

summed at the FILTER pin and used to generate the

received-signal-strength indication (RSSI). The RSSI

output voltage is linearly proportional to the input power

(in decibels), and is approximated by:

The RSSI output is insensitive to fluctuations in temperature

and supply voltage. The power detector functions as a

broadband power meter that detects the total power of all

signals present in the passband of approximately 750MHz.

Refer to the Typical Operating Characteristics graphs show-

ing RSSI output versus input power and signal amplitude.

The high-speed RSSI signal is filtered with one external

ance at the FILTER pin is approximately 500

Ω.

Input-Offset Correction

The limiting amplifier provides approximately 60dB of

gain. An input DC offset of even 1mV reduces the

power-detection circuit’s accuracy and can cause the

output to limit. A low-frequency feedback loop is inte-

grated into the MAX3761/MAX3762 to remove input off-

set. DC coupling the inputs is not recommended, as

this prevents the DC-offset-correction circuitry from

functioning properly. Input offset is typically reduced to

less than 100µV.

The capacitance between pins CZP and CZN, in parallel

with a 10pF integrated capacitance, determines the off-

set-correction circuit’s time constant. The input imped-

ance between CZP and CZN is approximately 800k

Ω.

The offset correction circuitry requires an average data-

input duty cycle of 50%. If the input data has a different

average duty cycle, the output will have increased

pulse-width distortion.

V

(V) = 1.13 + 0.457log (V )

RSSI

IN

LIMITER

FWD

LIMITER

FWD

LIMITER

FWD

FILTER

REF

INV

VTH

R1

R2

GNDO

LOS+/LOS-

RSSI

50

Ω

OUT+/OUT-

DISABLE

VCCO

EN

CZN

CZP

SUB

GND

VIN+/VIN-

FWD = FULL-WAVE DETECTOR

LIMITER

FWD

MAX3761/MAX3762

Figure 1. Functional Diagram