11

LTC692/LTC693

Power Fail Warning

The LTC692/LTC693 generate a Power Failure Output

(PFO) for early warning of failure in the microprocessor's

power supply. This is accomplished by comparing the

Power Failure Input (PFI) with an internal 1.3V reference.

PFO goes low when the voltage at the PFI pin is less than

1.3V. Typically PFI is driven by an external voltage divider

(R1 and R2 in Figures 8 and 9) which senses either an

unregulated DC input or a regulated 5V output. The voltage

divider ratio can be chosen such that the voltage at the PFI

pin falls below 1.3V, several milliseconds before the 5V

supply falls below the maximum reset voltage threshold of

4.50V. PFO is normally used to interrupt the microproces-

sor to execute shutdown procedure between PFO and

RESET or RESET.

The power fail comparator, C3, does not have hysteresis.

Hysteresis can be added however, by connecting a resis-

tor between the PFO output and the noninverting PFI input

pin as shown in Figures 8 and 9. The upper and lower trip

points in the comparator are established as follows:

When PFO output is low, R3 sinks current from the

summing junction at the PFI pin.

When PFO output is high, the series combination of R3 and

R4 source current into the PFI summing junction.

Example 1: The circuit in Figure 8 demonstrates the use of

the power fail comparator to monitor the unregulated

power supply input. Assuming the the rate of decay of the

200mV. With these assumptions in mind, we can reason-

maximum reset voltage threshold and the dropout voltage

S

APPLICATI

I FOR ATIO

Figure 6. A Typical Nonvolatile CMOS RAM Application

5V

3V

0.1

µF

10

µF

LTC693

GND

LTC692/3 • F06

RESET

CE IN

CE OUT

RESET

0.1

µF

TO

µP

FROM DECODER

CS

20ns PROPAGATION DELAY

62512

RAM

+

GND

Figure 7. Write Protect for RAM with the LTC692

5V

3V

0.1

µF

10

µF

LTC692

GND

LTC692/3 • F07

RESET

0.1

µF

CS

62128

RAM

CS1

CS2

GND

+

V = 1.3V 1+

R1

R2

R1

R3

H

+









V

1.3V 1

R1

R2

–

(5V – 1.3V)R1

1.3V(R3 R4)

+









Assuming R4

R3,V

5V

R1

R3

HYSTERESIS

<<

=

10

µF

10

µF

ADJ

LTC692/3 • F09

0.1

µF

TO

µP

LT1086-5

R4

10k

+

R1

27k

R3

2.7M

R2

8.2k

+

5V

R5

3.3k

GND

PFO

PFI

LTC692

LTC693

Figure 9. Monitoring

Regulated DC Supply

with the LTC692/LTC693 Power Fail Comparator

10

µF

100

µF

ADJ

LTC692/3 • F08

0.1

µF

TO

µP

PFO

GND

LT1086-5

R4

10k

PFI

LTC692

LTC693

R1

51k

R2

10k

R3

300k

++

5V

Figure 8. Monitoring

Unregulated DC Supply with the

LTC692/LTC693 Power Fail Comparator