LTC2400CS8 datasheet(16/40 Pages) LINER

16 / 40 page

LTC2400

External Serial Clock, 2-Wire I/O

This timing mode utilizes a 2-wire serial I/O interface. The

conversion result is shifted out of the device by an exter-

nally generated serial clock (SCK) signal, see Figure 7. CS

may be permanently tied to ground (Pin 4), simplifying the

user interface or isolation barrier.

The external serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

approximately 0.5ms after VCC exceeds 2.2V. The level

applied to SCK at this time determines if SCK is internal or

external. SCK must be driven LOW prior to the end of POR

in order to enter the external serial clock timing mode.

Since CS is tied LOW, the end-of-conversion (EOC) can be

continuously monitored at the SDO pin during the convert

and sleep states. EOC may be used as an interrupt to an

external controller indicating the conversion result is

ready. EOC = 1 while the conversion is in progress and EOC

= 0 once the conversion enters the low power sleep state.

On the falling edge of EOC, the conversion result is loaded

into an internal static shift register. The device remains in

the sleep state until the first rising edge of SCK. Data is

APPLICATIONS INFORMATION

shifted out the SDO pin on each falling edge of SCK

enabling external circuitry to latch data on the rising edge

of SCK. EOC can be latched on the first rising edge of SCK.

On the 32nd falling edge of SCK, SDO goes HIGH (EOC =

1) indicating a new conversion has begun.

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 8.

In order to select the internal serial clock timing mode, the

serial clock pin (SCK) must be floating (HI-Z) or pulled

HIGH prior to the falling edge of CS. The device will not

enter the internal serial clock mode if SCK is driven LOW

on the falling edge of CS. An internal weak pull-up resistor

is active on the SCK pin during the falling edge of CS;

therefore, the internal serial clock timing mode is auto-

matically selected if SCK is not externally driven.

The serial data output pin (SDO) is HI-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

VCC

VREF

SCK

VIN

SDO

GND

VREF

0.1V TO VCC

VIN

–0.12VREF TO 1.12VREF

= 50Hz REJECTION

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

µF

2.7V TO 5.5V

LTC2400

SDO

SCK

(EXTERNAL)

DATA OUTPUT

CONVERSION

SLEEP

TEST EOC

DATA OUTPUT

Hi-Z

CONVERSION

2400 F06

MSB

EXR

SIG

BIT 8

BIT 27

BIT 9

BIT 28

BIT 29

BIT 30

EOC

BIT 31

BIT 0

EOC

Hi-Z

VCC

TEST EOC

Figure 6. External Serial Clock, Reduced Data Output Length

LTC2400CS8 датащи(PDF) 16 Page - Linear Technology

LTC2400CS8 датащи(HTML) 16 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

датащи скачать

ссылки URL