LTC1400CS8 datasheet(7/20 Pages) LINER

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LTC1400

APPLICATIONS INFORMATION

Conversion Details

The LTC1400 uses a successive approximation algorithm

and an internal sample-and-hold circuit to convert an

analog signal to a 12-bit serial output based on a precision

internal reference. The control logic provides easy inter-

face to microprocessors and DSPs through 3-wire con-

nections.

A rising edge on the CONV input starts a conversion. At the

start of a conversion the successive approximation regis-

ter (SAR) is reset. Once a conversion cycle has begun it

cannot be restarted.

During conversion, the internal 12-bit capacitive DAC

output is sequenced by the SAR from the most significant

bit (MSB) to the least significant bit (LSB). Referring to

Figure 1, the AIN input connects to the sample-and-hold

capacitor during the acquired phase and the comparator

offset is nulled by the feedback switch. In this acquire

phase, it typically takes 200ns for the sample-and-hold

capacitor to acquire the analog signal. During the convert

phase, the comparator feedback switch opens, putting the

comparator into the compare mode. The input switches

connect CSAMPLE to ground, injecting the analog input

charge onto the summing junction. This input charge is

successively compared with the binary-weighted charges

supplied by the capacitive DAC. Bit decisions are made by

the high speed comparator. At the end of a conversion, the

DAC output balances the AIN input charge. The SAR

contents (a 12-bit data word) which represent the input

voltage, are output through the serial pin DOUT.

Dynamic Performance

The LTC1400 has excellent high speed sampling capabil-

ity. FFT (Fast Fourier Transform) test techniques are used

to test the ADC’s frequency response, distortion and noise

at the rated throughput. By applying a low distortion sine

wave and analyzing the digital output using an FFT algo-

rithm, the ADC’s spectral content can be examined for

frequencies outside the fundamental. Figure 2a shows a

typical LTC1400 FFT plot.

Signal-to-Noise Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is the

ratio between the RMS amplitude of the fundamental input

frequency to the RMS amplitude of all other frequency

components at the A/D output. The output is band limited

to frequencies from DC to half the sampling frequency.

Figure 2a shows a typical spectral content with a 400kHz

sampling rate and a 100kHz input. The dynamic perfor-

mance is excellent for input frequencies up to the Nyquist

limit of 200kHz as shown in Figure 2b.

Figure 1. AIN Input

LTC1400 • F01

SAMPLE

DOUT

CDAC

VDAC

DAC

AIN

CSAMPLE

COMP

SAMPLE

HOLD

Figure 2a. LTC1400 Nonaveraged, 4096 Point FFT

Plot with 100kHz Input Frequency in Bipolar Mode

FREQUENCY (kHz)

80 100

140

180

120

160

200

LTC1400 • F02a

–10

–20

–30

–40

–50

– 60

–70

–80

–90

–100

–110

–120

fSAMPLE = 400kHz

fIN = 94.824kHz

SINAD = 72.5dB

THD = – 82dB

Effective Number of Bits

The effective number of bits (ENOBs) is a measurement of

the effective resolution of an ADC and is directly related to

the S/(N + D) by the equation:

SN D

()

/– .

176

602

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