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LTC1282ACSW датащи(PDF) 19 Page - Linear Technology

номер детали LTC1282ACSW
подробное описание детали  3V 140ksps 12-Bit Sampling A/D Converter with Reference
PDF  24 Pages
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производитель  LINER [Linear Technology]
домашняя страница  http://www.linear.com
Logo LINER - Linear Technology

LTC1282ACSW датащи(HTML) 19 Page - Linear Technology

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19
LTC1282
S
APPLICATI
I FOR ATIO
Figure 19. ROM Mode Two Byte Read Timing Diagram
Table 5. ROM Mode, Two Byte Read Data Bus Status
Data Outputs
D7
D6
D5
D4
D3/11
D2/10
D1/9
D0/8
First Read (Old Data)
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Second Read (New Data)
Low
Low
Low
Low
DB11
DB10
DB9
DB8
Third Read (New Data)
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
OLD DATA
DB7-DB0
NEW DATA
DB11-DB8
TRACK
HOLD
DATA
BUSY
RD
CS
RD
LTC1282 • F19
t8
t1
t2
t3
tCONV
t11
t9
t8
t9
t5
t1
t4
t5
t10
t3
t7
t3
t7
t12
t12
HBEN
t7
t4
t1
t8
t9
NEW DATA
DB7-DB0
t2
t4
t5
where D is Data Memory Address and PA is the PORT
ADDRESS.
MC68000 Microprocessor
Figure 21 shows a typical interface for the MC68000. The
LTC1282 is operating in the Slow Memory Mode. Assum-
ing the LTC1282 is located at address C000, then the
following single 16-bit MOVE instruction both starts a
conversion and reads the conversion result:
Move.W $C000,D0
At the beginning of the instruction cycle when the ADC
address is selected, BUSY and CS assert DTACK so that
the MC68000 is forced into a WAIT state. At the end of
conversion, BUSY returns high and the conversion result
is placed in the D0 register of the microprocessor.
Figure 20. TMS320C25 Interface
DATA BUS
LTC1282 • F20
ADDRESS BUS
D0
D16
R/W
READY
IS
A1
A16
TMS320C25
ADDRESS
DECODE
EN
D0/8
D11
RD
BUSY
CS
HBEN
LTC1282
ADDITIONAL PINS OMITTED FOR CLARITY



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