LTC1282ACSW datasheet(10/24 Pages) LINER

10 / 24 page

LTC1282

FU TIO AL BLOCK DIAGRA

APPLICATI

I FOR ATIO

CONVERSION DETAILS

The LTC1282 uses a successive approximation and an

internal sample-and-hold circuitry to convert an analog

signal to a 12-bit parallel or 2-byte output. The ADC is

complete with a precision reference and an internal clock.

The control logic provides easy interface to microproces-

sors and DSPs. Please refer to the Digital Interface section

for the data format.

Conversion start is controlled by the CS, RD and HBEN

inputs. At the start of conversion the successive approxi-

mation register (SAR) is reset and the three-state data

outputs are enabled. Once a conversion cycle has begun

it cannot be restarted.

During conversion, the internal 12-bit capacitive DAC

output is sequenced by the SAR from the most significant

bit (MSB) to the least significant bit (LSB). Referring to

Figure 1, the AIN input connects to the sample-and-hold

capacitor during the sample phase, and the comparator

offset is nulled by the feedback switch. In this sample

phase, a minimum delay of 1.14

µs will provide enough

time for the sample-and-hold capacitor to acquire the

analog signal. During the convert phase, the comparator

feedback switch opens, putting the comparator into the

compare mode. The input switch switches CSAMPLE to

ground, injecting the analog input charge to the summing

junction. This input charge is successively compared with

the binary-weighted charges supplied by the capacitive

DAC. Bit decisions are made by the high speed comparator.

At the end of a conversion, the DAC output balances the AIN

input charge. The SAR contents (a 12-bit data word) which

represent the AIN are loaded into the 12-bit latch.

VDAC

LTC1282 • F01

–

CDAC

DAC

SAMPLE

HOLD

CSAMPLE

12-BIT

LATCH

COMPARATOR

SAMPLE

AIN

Figure 1. AIN Input

CSAMPLE

CONTROL

LOGIC

INTERNAL

CLOCK

SUCCESSIVE

APPROXIMATION

OUTPUT

LATCHES

•

D11

D0/8

BUSY

1.2V

REFERENCE

VREF(OUT)

DGND

AGND

AIN

SAMPLE

HOLD

SAMPLE

VSS (–3V FOR BIPOLAR MODE,

AGND FOR UNIPOLAR MODE)

VDD

HBEN

LTC1282 • FBD

12-BIT

CAPACITIVE

DAC

COMPARATOR

LTC1282ACSW датащи(PDF) 10 Page - Linear Technology

LTC1282ACSW датащи(HTML) 10 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

датащи скачать

ссылки URL