7

LTC1143/LTC1143L

LTC1143L-ADJ

The LTC1143 series consists of two individual regulator

blocks, each using current mode, constant off-time archi-

tectures to switch an external power MOSFET. The two

LTC1143/LTC1143L regulators are internally set for 3.3V

and 5V, while the two LTC1143L-ADJ regulators have

externally programmable output voltages. Operating fre-

quency is individually set on each section by external

capacitors at the timing capacitor Pins 6 and 14.

The output voltage is sensed by voltage comparator V and

gain block G, which compare the divided output voltage

with a reference voltage of 1.25V. To optimize efficiency,

the LTC1143 series automatically switches between two

modes of operation, burst and continuous. The voltage

comparator is the primary control element when the

device is in Burst Mode operation, while the gain block

controls the output voltage in continuous mode.

During the switch “ON” cycle in continuous mode, current

comparator C monitors the voltage between Pins 1 (9) and

16 (8) connected across an external shunt in series with

the inductor. When the voltage across the shunt reaches

turning off the P-channel MOSFET. The timing capacitor

connected to Pin 14 (6) is now allowed to discharge at a

rate determined by the off-time controller. The discharge

current is made proportional to the feedback voltage to

model the inductor current, which decays at a rate that is

also proportional to the output voltage.

When the voltage on the timing capacitor has discharged

causes the P-drive output to go low, turning the P-channel

MOSFET back on. The cycle then repeats.

As the load current increases, the output voltage

decreases slightly. This causes the output of the gain

stage [Pin 15 (7)] to increase the current comparator

threshold, thus tracking the load current.

The sequence of events for Burst Mode operation is very

similar to continuous operation with the cycle interrupted

by the voltage comparator. When the output voltage is at

or above the desired regulated value, the P-channel

MOSFET is held off by comparator V and the timing

tor S trips, causing the internal sleep line to go low.

–

+

–

+

REFERENCE

4(12)

P-DRIVE

GROUND

–

+

V

–

+

C

25mV TO 150mV

+

–

1(9)

2(10)

SHUTDOWN

(LTC1143/LTC1143L)

(LTC1143L-ADJ)

100k

X

X

16(8)

1.25V

5pF

G

15(7)

Q

R

S

OFF-TIME

CONTROL

14(6)

13k

–

+

S

SLEEP

T

1143 FD

13(5)

3(11)

Only one regulator block shown. Connections shown for LT1143/LTC1143L; changes create LTC1143L-ADJ