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LTC1143CS датащи(PDF) 16 Page - Linear Technology |
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LTC1143CS датащи(HTML) 16 Page - Linear Technology |
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16 / 20 page ![]() 16 LTC1143/LTC1143L LTC1143L-ADJ APPLICATIONS INFORMATION 5) Is the VIN decoupling capacitor (1µF, 0.1µF) con- nected closely between Pin 13 (5) and GND Pin 3 (11)? This capacitor carries the MOSFET driver peak currents. 6) For the LTC1143 and LTC1143L, are the SHUT- DOWN Pins 2 and 10 actively pulled to ground during normal operation? Both SHUTDOWN pins are high impedance and must not be allowed to float. Both pins can be driven by the same external signal if needed. 7) For the LTC1143L-ADJ, are the VFB Pins 2 and 10 decoupled with 100pF as close to the device as possible? The VFB line is sensitive to noise pickup and should be kept away from the P-channel MOSFET. Figure 9. LTC1143 Layout Diagram (see Board Layout Checklist) + + COUT5 CIN3 VOUT5 + – RSENSE5 RSENSE3 L1 L2 P-CH D1 D2 1k *MUST BE LOCATED CLOSE TO LTC1143 SHUTDOWN (3.3V OUTPUT) CT5 P-CH CIN5 COUT3 VIN3 VIN5 BOLD LINES INDICATE HIGH CURRENT PATHS SHUTDOWN (5V OUTPUT) + VOUT3 + – + – 1000pF* 1000pF* 0.0033 µF 1k CT3 0.0033 µF + – 0.22 µF* 0.22 µF* VIN5 VIN3 + 1143 F09 |
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