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LTC1143CS датащи(PDF) 15 Page - Linear Technology

номер детали LTC1143CS
подробное описание детали  Dual High Efficiency SO-16 Step-Down Switching Regulator Controllers
PDF  20 Pages
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производитель  LINER [Linear Technology]
домашняя страница  http://www.linear.com
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LTC1143CS датащи(HTML) 15 Page - Linear Technology

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LTC1143/LTC1143L
LTC1143L-ADJ
APPLICATIONS INFORMATION
With the addition of R3 a current is generated though R1,
causing an offset of:
VV
R
RR
OFFSET
OUT
=
+


1
13
If VOFFSET > 25mV, the built-in offset will be cancelled and
Burst Mode operation is prevented from occurring. Since
VOFFSET is constant, the maximum load current is also
decreased by the same offset. Thus, to get back to the
same IMAX, the value of the sense resistor must be lower:
R
mV
I
SENSE
MAX
≈
75
To prevent noise spikes from erroneously tripping the
current comparator, a 1000pF capacitor is needed across
Pins 1 (16) and 9 (8).
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1143 series. These items are also illustrated graphi-
cally in the layout diagram of Figure 9. In general, each
block should be self-contained with little cross coupling
for best performance. Check the following in your layout:
1) Are the signal and power grounds segregated? The
LTC1143 series GND Pin 3 (11) must return separately
to: a) the power and b) the signal grounds. The
power ground returns to the anode of the Schottky
diode and (–) plate of CIN, which should have as short
lead lengths as possible.The signal ground (b) con-
nects to the (–) plate of COUT.
2) Does the LTC1143 series SENSE– Pin 16 (8) connect
to a point close to RSENSE and the (+) plate of COUT?
3) Are the SENSE– and SENSE+ leads routed together
with minimum PC trace spacing? The 1000pF
capacitor between Pins 1 (9) and 16 (8) should be as
close as possible to the LTC1143 series.
4) Does the (+) plate of CIN connect to the source of the
P-channel MOSFET as closely as possible? This
capacitor provides the AC current to the P-channel
MOSFET.
3.3V
0V
(a) CONTINUOUS MODE OPERATION
3.3V
0V
(b) Burst Mode OPERATION
LTC1143 • F07
Figure 7. CT Waveforms
Auxiliary Windings––Suppressing Burst Mode
Operation
The LTC1143 series operates nonsynchronously with the
normal limitation that the power drawn from the inductor
primary winding must not be less than twice the power
drawn from the auxiliary windings. (With synchronous
switching, using the LTC1142 series, auxiliary outputs
may be loaded without regard to the primary output load,
providing that the loop remains in continuous mode
operation.)
Burst Mode operation can be suppressed at low output
currents with a simple external network that cancels the
25mV minimum current comparator threshold. This tech-
nique is also useful for eliminating audible noise from
certain types of inductors in high current (IOUT > 5A)
applications when they are lightly loaded.
An external offset is put in series with the Sense– pin to
subtract from the built-in 25mV offset. An example of this
technique is shown in Figure 8. Two 100
Ω resistors are
inserted in series with the sense leads from the sense
resistor.
RSENSE
1000pF
R2
100
Ω
R1
100
Ω
R3
+
COUT
VOUT
SENSE+
[PIN 16 (8)]
SENSE –
[PIN 1(9)]
1143 F08
Figure 8. Suppression of Burst Mode Operation



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