LT1339C datasheet(15/20 Pages) LINER

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LT1339

APPLICATIONS INFORMATION

∆VOUT ≈ ∆IL{ESR + [(4)(fO) • COUT]–1}

where fO = operating frequency.

Efficiency Considerations and Heat Dissipation

High output power applications have inherent concerns

regarding power dissipation in converter components.

Although high efficiencies are achieved using the LT1339,

the power dissipated in the converter climbs to relatively

high values when the load draws large amounts of power.

Even at 90% efficiency, an application that provides 500W

to the load has conversion loss of 55W.

I2R dissipation through the switches, sense resistor and

inductor series resistance create substantial losses under

high currents. Generally, the dominant I2R loss is evident

in the FET switches. Loss in each switch is proportional to

the conduction time of that switch. For example, in a 48V

to 5V converter the synchronous FET conducts load cur-

rent for almost 90% of the cycle time and thus, requires

greater consideration for dissipating I2R power.

Gate charge/discharge current creates additional current

drain on the 12V supply. If powered from a high voltage

input through a linear regulator, the losses in that regula-

tor device can become significant. A supply solution

bootstrapped from the output would draw current from a

lower voltage source and reduce this loss component.

Transition losses are significant in the topside switch FET

when high VIN voltages are used. Transition losses can be

estimated as:

PTLOSS ≈ 2(VIN)

2(IMAX)(CRSS)(fO)

Since the conduction time in the main switch of a 48V to

5V converter is small, the I2R loss in the main switch FET

is also small. However, since the FET gate must switch up

past the 48V input voltage, transition loss can become a

significant factor. In such a case, it is often prudent to take

the increased I2R loss of a smaller FET in order to reduce

CRSS and thus, the associated transition losses.

Gate Drive Buffers

The LT1339 is designed to drive relatively large capacitive

loads. However, in certain applications, efficiency im-

provements can be realized by adding an external buffer

stage to drive the gates of the FET switches. When the

The maximum power loss terms for the switches are thus:

PMAIN = (DC)(IMAX)

2(1 +

δ)(RDS(ON)) +

2(VIN)

2(IMAX)(CRSS)(fO)

PSYNC = (1 – DC)(IMAX)

2(1 +

δ)(RDS(ON))

The (1 +

δ) term in the above relations is the temperature

dependency of RDS(ON), typically given in the form of a

normalized RDS(ON) vs Temperature curve in a MOSFET

data sheet.

In some applications, parasitic FET capacitances couple

the negative going switch node transient onto the bottom

gate drive pin of the LT1339, causing a negative voltage in

excess of the Absolute Maximum Rating to be imposed on

that pin. Connection of a catch Schottky (rated to about 1A

is typically sufficient) from this pin to ground will eliminate

this effect.

CIN and COUT Supply Decoupling Capacitor Selection

The large currents typical of LT1339 applications require

special consideration for the converter input and output

supply decoupling capacitors. Under normal steady state

operation, the source current of the main switch MOSFET

is a square wave of duty cycle VOUT/VIN. Most of this

current is provided by the input bypass capacitor. To

prevent large input voltage transients and avoid bypass

capacitor heating, a low ESR input capacitor sized for the

maximum RMS current must be used. This maximum

capacitor RMS current follows the relation:

RMS

MAX

OUT

≈ ()

(

)

()

–

which peaks at a 50% duty cycle, when IRMS = IMAX/2.

Capacitor ripple current ratings are often based on only

2000 hours (three months) lifetime; it is advisable to

derate either the ESR or temperature rating of the capaci-

tor for increased MTBF of the regulator.

The output capacitor in a buck converter generally has

much less ripple current than the input capacitor. Peak-to-

peak ripple current is equal to that in the inductor (

∆IL),

typically a fraction of the load current. COUT is selected to

reduce output voltage ripple to a desirable value given an

expected output ripple current. Output ripple (

∆VOUT) is

approximated by:

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