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AN4570 датащи(PDF) 41 Page - STMicroelectronics

номер детали AN4570
подробное описание детали  This application note describes how to use the high-density
PDF  46 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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AN4570 датащи(HTML) 41 Page - STMicroelectronics

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AN4570
Interfacing with an 8-bit NAND Flash memory
45
4.4
Error correction code computation
4.4.1
Error correction code (ECC) computation overview
The FMC NAND Flash controller includes two pieces of error correction code computation
hardware, one for each NAND Flash memory block.
The ECC can be performed for page sizes of 256, 512, 1024, 2048, 4096 or 8192 bytes,
depending on the ECC page size configured by the user. Depending on the configured page
size, the ECC code will be 22, 24, 26, 28, 30 or 32 bits.
To even improve the error coverage, the user can read/write the NAND Flash page with a
reduced ECC page size. This is possible when starting and stopping the ECC computation
after the desired number of bytes to check. In this case, the ECC code is only calculated for
the bytes written and read.
The error correction code algorithm implemented in the FMC can perform 1-bit error
correction and 2-bit error detection per page read from or written to the NAND Flash
memory. It is based on the Hamming algorithm and consists in calculating the row and
column parity.
4.4.2
Error detection
Figure 12. Error detection flowchart
Program NAND page operation successful
Read ECC value during Program operation
Read written NAND page
Read new ECC value during Read operation
XOR operation between the two ECC values
All ECC bits
are zero
Yes
No
No error
Error detected
ai15185



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