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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AN4570 датащи(PDF) 22 Page - STMicroelectronics |
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AN4570 датащи(HTML) 22 Page - STMicroelectronics |
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22 / 46 page  Interfacing with a non-multiplexed, asynchronous 16-bit SRAM AN4570 22/46 DocID026804 Rev 1 3 Interfacing with a non-multiplexed, asynchronous 16- bit SRAM 3.1 FMC configuration SRAM and NOR Flash memories share the same FMC banks. The protocol to be used depends on the selected memory type. To control an SRAM, the FMC provides the following possible features: • Enable or disable the address/data multiplexing feature • Select the memory type to be used: NOR/SRAM/PSRAM • Define the external memory data bus width: 8/16 bits • Enable or disable the extended mode: this mode is used to access the memory with a different timing configuration for read and write operations. Like for NOR Flash memories, the user has to compute and set the following parameters as a function of the information in the SRAM datasheet: ADDSET: address setup time DATAST: data setup time Figure 6 and Figure 7 show the different timings for a typical SRAM access. Figure 6. SRAM asynchronous read access timing |
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