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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PM0223 датащи(PDF) 83 Page - STMicroelectronics |
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PM0223 датащи(HTML) 83 Page - STMicroelectronics |
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83 / 110 page  DocID025763 Rev 1 83/110 PM0223 STM32L0 Core Peripherals 108 4.2.2 Interrupt Set-enable Register The NVIC_ISER enables interrupts, and shows which interrupts are enabled. See the register summary in Table 26 on page 82 for the register attributes. The bit assignments are: If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. 4.2.3 Interrupt Clear-enable Register The NVIC_ICER disables interrupts, and show which interrupts are enabled. See the register summary in Table 26 on page 82 for the register attributes. The bit assignments are: void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)(1) Sets the priority of an interrupt or exception with configurable priority level to 1. uint32_t NVIC_GetPriority(IRQn_Type IRQn)(1) Reads the priority of an interrupt or exception with configurable priority level. This function return the current priority level. 1. The input parameter IRQn is the IRQ number, see Table 13 on page 27 for more information. Table 27. CMSIS access NVIC functions (continued) CMSIS function Description 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SETPENA[31:16] rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SETPENA[15:0] rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs Bits 31:0 SETENA: Interrupt set-enable bits Write: 0: No effect 1: Enable interrupt Read: 0: Interrupt disabled 1: Interrupt enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CLRENA[31:16] rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLRENA[15:0] rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 |
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