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AN4206 датащи(PDF) 22 Page - STMicroelectronics

номер детали AN4206
подробное описание детали  Getting started with STM32F3 series hardware development
PDF  34 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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AN4206 датащи(HTML) 22 Page - STMicroelectronics

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Debug management
AN4206
22/34
DocID023944 Rev 4
4.3.3
Internal pull-up and pull-down resistors on JTAG pins
The JTAG input pins must not be floating since they are directly connected to flip-flops to
control the debug mode features. Special care must be taken with the SWCLK/TCK pin that
is directly connected to the clock of some of these flip-flops.
To avoid any uncontrolled I/O levels, the STM32F3xx embeds internal pull-up and pull-down
resistors on JTAG input pins:
JNTRST: Internal pull-up
JTDI: Internal pull-up
JTMS/SWDIO: Internal pull-up
TCK/SWCLK: Internal pull-down
Once a JTAG I/O is released by the user software, the GPIO controller takes control again.
The reset states of the GPIO control registers put the I/Os in the equivalent state:
JNTRST: Input pull-up
JTDI: Input pull-up
JTMS/SWDIO: Input pull-up
JTCK/SWCLK: Input pull-down
JTDO: Input floating
The software can then use these I/Os as standard GPIOs.
Note:
The JTAG IEEE standard recommends to add pull-up resistors on TDI, TMS and nTRST but
there is no special recommendation for TCK. However, for the STM32F3xx, an integrated
pull-down resistor is used for JTCK.
Having embedded pull-up and pull-down resistors removes the need to add external
resistors.



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