AN4206 datasheet(18/34 Pages) STMICROELECTRONICS

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Clocks

AN4206

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DocID023944 Rev 4

Calibration

RC oscillator frequencies can vary from one chip to another due to manufacturing process

variations, This is why each device is factory calibrated by ST for 1% accuracy at TA = 25 °C.

Furthermore, it is possible to route the HSI clock to the MCO multiplexer. The clock can then

be the input to Timer 16 in all STM32F3 series devices (except the STM32F373 line where

the clock is the input to Timer 14) to allow the user to calibrate the oscillator.

2.4

LSI clock

The LSI RC acts as an low-power clock source that can be kept running in Stop and

Standby mode for the independent watchdog (IWDG) and RTC. The clock frequency is

around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to the electrical

characteristics section of the datasheets.

2.5

Clock security system (CSS)

The clock security system can be activated by software. In this case, the clock detector is

enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.



If a failure is detected on the HSE oscillator clock, the oscillator is automatically

disabled.

–

A clock failure event is sent to the break inputs of:



- TIM1/8/15/16/17 in the STM32F303xB/C and STM32F358 devices.



- TIM1/8/20/15/16/17 in the STM32F303xD/E and STM32F398 devices.



- TIM1/15/16/17 in the STM32F301/302/303x6/8, STM32F302xB/C/D/E,

STM32F334, STM323F318 and STM32F328 devices.

–

An interrupt is generated to inform the software about the failure (clock security

system interrupt CSSI), allowing the MCU to perform recovery operations.

–

CSSI is linked to the Cortex®-M4 NMI (non-maskable interrupt) exception vector.



If the HSE oscillator is used directly or indirectly as the system clock (indirectly means

that it is used as the PLL input clock, and the PLL clock is used as the system clock), a

detected failure causes a switch of the system clock to the HSI oscillator and the

disabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the

clock entry of the PLL that is being used as a system clock when the failure occurs, the

PLL is disabled too.

For details, see the STM32F3 reference manuals (RM0316, RM0313, RM0364, RM0365

and RM0366) available from STMicroelectronics website www.st.com.

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