Debug management

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Debug management

4.1

Introduction

The Host/Target interface is the hardware equipment that connects the host to the

application board. This interface is made of three components: a hardware debug tool, a

JTAG or SWD connector and a cable connecting the host to the debug tool.

Figure 10 shows the connection of the host to the STM32F3xx evaluation board.

Figure 10. Host-to-board connection

4.2

SWJ debug port (serial wire and JTAG)

The STM32F3 series core integrates the serial wire / JTAG debug port (SWJ-DP). It is an

SW-DP (2-pin) interface.



The JTAG debug port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP-

AP port



The serial wire debug port (SW-DP) provides a 2-pin (clock + data) interface to the

AHP-AP port

In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG

pins of the JTAG-DP.

4.3

Pinout and debug port pins

The STM32F3 series MCU is offered in various packages with different numbers of

available pins. As a result, some functionality related to the pin availability may differ from

one package to another.