AN4088 datasheet(14/71 Pages) STMICROELECTRONICS

14 / 71 page

Peripheral migration

AN4088

14/71

DocID023072 Rev 3

3.4

Reset and clock controller (RCC) interface

The main differences related to the RCC (Reset and clock controller) in the STM32F0 series

versus STM32F1 series are presented in Table 9.

CAN2

APB1

0x40006800

CAN1

0x40006400

UART5

0x40005000

SPI3/I2S3

0x40003C00

TIM13

0x40001C00

TIM12

0x40001800

TIM5

0x40000C00

BKP registers

0x40006C00

AFIO

APB2

0x40010000

1. NA in table cells with gray shading = feature not available.

STM32F0 series devices have only one APB bus, APB1 and APB2 indicate on which APB register the clock configuration

bits of those peripherals are defined.

Table 8. IP bus mapping differences between STM32F0 and STM32F1 series(1) (continued)

Peripheral

STM32F0 series

STM32F1 series

Bus

Base address

Bus

Base address

Table 9. RCC differences between STM32F1 and STM32F0 series

RCC

STM32F1 series

STM32F0 series

HSI 48

High speed internal oscillator at 48MHz

HSI 14

High speed internal oscillator dedicated to

ADC

HSI

8 MHz RC factory-trimmed

Similar

LSI

40 kHz RC

Similar

HSE

3 - 25 MHz

Depending on the product line used

4 - 32 MHz(1)

LSE

32.768 kHz

Similar

PLL

– Connectivity line: main PLL + 2 PLLs for

I2S, Ethernet and OTG FS clock

– Other product lines: main PLL

Main PLL

System clock source HSI, HSE or PLL

HSI48, HSI, HSE or PLL

System clock

frequency

– Up to 72 MHz depending on the product

line used,

– 8 MHz after reset using HSI

– Up to 48 MHz depending on the product

line used

– 8 MHz after reset using HSI(1)

APB1/APB frequency Up to 36 MHz

Up to 48 MHz(1)

RTC clock source

LSI, LSE or HSE/128

LSI, LSE or HSE clock divided by 32

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