RM0312 datasheet(262/275 Pages) STMICROELECTRONICS

262 / 275 page

ProxSense™ (PXS)

RM0312

262/275

DocID022352 Rev 3

22.9.5

ProxSense Clock Control Register 1 (PXS_CKCR1)

Address offset: 0x06

Reset value: 0x30

Bit 3 SYNCPF: Synchronization (SYNC) pending flag

0: The ProxSense peripheral does not wait for an active edge on the PXS_TRIG input

1: The ProxSense peripheral waits for an active edge on the PXS_TRIG input

This status bit is set by hardware when the START bit is set and when the SYNC feature is enabled

(SYNCEN = 1 and PXSEN = 1). It is cleared by hardware when the selected edge (as specified by

SYNCEDGE) occurs, at which time a conversion is launched.

Bit 2 SYNC_OVRF: Synchronization (SYNC) overflow flag

0: No SYNC overflow occurs

1: A SYNC overflow occurs

There is a “SYNC overflow” if the selected edge occurs on PXS_TRIG pin while SYNCEN = 1,

SYNCPF = 0, and PXSEN = 1. Such edges are ignored and the status bit SYNC_OVRF is set. There

is not necessarily a problem when SYNC_OVRF = 1 as this just indicates that no conversion was

launched on an PXS_TRIG active edge.

Bits 1:0 Reserved

76543210

Reserved

PRESC[2:0]

Reserved

ANADEAD

INCPHASE

Bit 7 Reserved

Bits 6:4 PRESC[2:0]: Frequency selection for ProxSense clock

000: 125 kHz

001: 250 kHz

010: 500 kHz

011: 1 MHz (default after reset)

100: 2 MHz

101: 4 MHz

110: 8 MHz

111: 16 MHz

Note: These bits can be modified only when PXSEN = 0.

Bits 3:2 Reserved

Bit 1 ANADEAD: Ensures the deadtime (non-overlap interval) between the UP and PASS phases using a

short analog delay rather than a half-cycle deadtime.

0: The deadtime between the UP and PASS phases is one half of a ProxSense clock cycle.

1: The deadtime between the UP and PASS phases is about 10 ns, and the length of the UP phase

is increased by one cycle.

Note: This bit can be modified only when CIPF = 0.

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