RM0312 datasheet(261/275 Pages) STMICROELECTRONICS

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RM0312

ProxSense™ (PXS)

273

22.9.4

ProxSense Interrupt and Status Register (PXS_ISR)

Address offset: 0x04

Reset value: 0x00

7654321

EOCF

FCCF

NOISEDETF

CIPF

SYNCPF

SYNC_OVRF

Reserved

Bit 7 EOCF: End of conversion flag

0: No end of conversion has occurred

1: End of conversion has occurred

This status bit is set by hardware when each of the enabled Rx channels has finished converting and

the results are ready.

EOCF is cleared by hardware when a conversion is launched (when CIPF becomes ‘1’) or when

PXSEN = 0.

If EOCITEN = 1, the ProxSense interrupt occurs when EOCF transitions to 1. EOCF must be cleared

by software before exiting the interrupt service routine.

Note: When clearing this flag, it is recommended to write 0x60 to this register to avoid accidentally

erasing the other flag bits. The BRES instruction is discouraged since an event may occur

between the read and write.

Bit 6 FCCF: First conversion completion flag

0: No first conversion completion interrupt has occurred

1: First conversion completion interrupt has occurred

This status bit is set by hardware the first time a channel conversion is completed after a conversion

has started. Subsequent conversion completions on other channels do not cause this bit to be set.

FCCF is cleared by hardware when a conversion is launched (when CIPF becomes ‘1’) or when

PXSEN = 0.

If FCCITEN = 1, the ProxSense interrupt occurs when FCCF rises. FCCF must be cleared by software

before exiting the interrupt service routine.

Note: When clearing this flag, it is recommended to write 0xA0 to this register to avoid accidentally

erasing the other flag bits. The BRES instruction is discouraged since an event may occur

between the read and write.

Bit 5 NOISEDETF: Noise detection flag

0: No noise detected

1: Noise detected

This status bit is set by hardware if RF noise is detected during a conversion. NOISEDETF is cleared

by software.

Note: When clearing this flag, it is recommended to write 0xC0 to this register to avoid accidentally

erasing the other flag bits. The BRES instruction is discouraged since an event may occur

between the read and write.

Bit 4 CIPF: Conversion in progress flag

0: No conversion is in progress

1: A conversion is in progress

This status bit is set by hardware when the START bit is set and it is cleared by hardware when the

conversion is completed. CIPF is read-only.

Note: Many control registers are locked (read-only) when CIPF = 1.

Note: If PXSEN is set to 0 (by software) during a conversion, the conversion is stopped. In this case,

CIPF remains at ‘1’ for as long as 8 µs after which it transitions to ‘0’.

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