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RM0312 датащи(PDF) 199 Page - STMicroelectronics

номер детали RM0312
подробное описание детали  STM8TL5xxx microcontroller family
PDF  275 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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RM0312 датащи(HTML) 199 Page - STMicroelectronics

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RM0312
Inter-integrated circuit (I2C) interface
200
19.7.14
TRISE register (I2C_TRISER)
Address offset: 0x0D
Reset value: 0x02
19.7.15
I2C register map and reset values
7
654
3210
Reserved
TRISE[5:0]
rw
Bits 7:6 Reserved
Bits 5:0 TRISE[5:0] Maximum rise time in Fast/Standard mode (Master mode)
These bits should provide the maximum duration of the SCL feedback loop in master mode. The
purpose is to keep a stable SCL frequency whatever the SCL rising edge duration.
These bits must be programmed with the maximum SCL rise time given in the I2C bus specification,
incremented by 1.
For instance: in standard mode, the maximum allowed SCL rise time is 1000 ns.
If the value in the I2C_FREQR register = 08h, then tMASTER = 125 ns therefore the TRISE[5:0] bits
must be programmed with 0x09.
(1000 ns / 125 ns = 8 + 1)
The filter value can also be added to TRISE[5:0].
If the result is not an integer, TRISE[5:0] must be programmed with the integer part, in order to
respect the tHIGH parameter.
Note: TRISE[5:0] must be configured only when the I2C is disabled (PE = 0).
Table 41. I2C register map
Address
offset
Register
name
7
6
5
432
1
0
0x00
I2C_CR1
Reset value
NO STRETCH
0
ENGC
0
-
0
-
0
-
0
-
0
-
0
PE
0
0x01
I2C_CR2
Reset value
SWRST
0
-
0
-
0
-
0
POS
0
ACK
0
STOP
0
START
0
0x02
I2C_FREQR
Reset value
-
0
-
0
FREQ[5:0]
000000
0x03
I2C_OAR1L
Reset value
ADD1[7:1]
0000000
ADD1[0]
0
0x04
I2C_OAR1H
Reset value
ADDMODE
0
ADDCONF
0
-
0
-
0
-
0
ADD1[9:8]
00
-
0
0x05
I2C_OAR2
Reset value
ADD2[7:1]
0
ENDUAL
0
0x06
I2C_DR
Reset value
DR[7:0]
0
0x07
I2C_SR1
Reset value
TXE
0
RXNE
0
-
0
STOPF
0
ADD10
0
BTF
0
ADDR
0
SB
0
0x08
I2C_SR2
Reset value
-
0
-
0
WUFH
0
-
0
OVR
0
AF
0
ARLO
0
BERR
0
0x09
I2C_SR3
Reset value
DUALF
0
-
0
-
0
GENCALL
0
-
0
TRA
0
BUSY
0
MSL
0



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