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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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RM0312 датащи(PDF) 202 Page - STMicroelectronics |
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RM0312 датащи(HTML) 202 Page - STMicroelectronics |
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202 / 275 page  Serial peripheral interface (SPI) RM0312 202/275 DocID022352 Rev 3 20.3 SPI functional description 20.3.1 General description The block diagram of the SPI is shown in Figure 72. Figure 72. SPI block diagram The SPI is connected to external devices through four pins: • MISO: Master In / Slave Out data (port C7). This pin can be used to transmit data in slave mode and receive data in master mode. • MOSI: Master Out / Slave In data (port C6). This pin can be used to transmit data in master mode and receive data in slave mode. • SCK: Serial Clock output (port C5) for SPI masters and Serial Clock input for SPI slaves. • NSS: Slave select (port E5). This is a optional pin to select a slave device. This pin acts as a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave NSS inputs can be driven by standard I/O ports on the master device. When configured in master mode (MSTR bit =1) and if NSS is pulled low, the SPI enters master mode fault state: the MSTR bit is automatically reset and the device is configured in slave mode (refer to Section 20.3.8: Error flags on page 216). A basic example of interconnections between a single master and a single slave is illustrated in Figure 73. RX BUFFER TX BUFFER SHIFT REGISTER LSBFirst READ WRITE ADDRESS AND DATA BUS MOSI MISO BAUD RATE GENERATOR SCK MASTER CONTROL LOGIC COMMUNICATION CONTROL SPE BR2 BR1 BR0 MSTRCPOL CPHA BR[2:0] RXIE LSB BIDI MODE BIDI OE RX SSM SSI OVR MOD RXNE TXE ERR TXIE WK 0 0 00 WKIE ONLY 0 1 NSS IE F UP FIRST BSY fMASTER 0 0 |
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