RM0312 datasheet(203/275 Pages) STMICROELECTRONICS

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RM0312

Serial peripheral interface (SPI)

223

Note:

When using the SPI in High-speed mode, the I/Os where SPI outputs are connected should

be programmed as fast slope outputs in order to be able to reach the expected bus speed.

Figure 73. Single master/ single slave application

The MOSI pins are connected together and the MISO pins are connected together. In this

way data is transferred serially between master and slave (most significant bit first).

The communication is always initiated by the master. When the master device transmits

data to a slave device via MOSI pin, the slave device responds the MISO pin. This implies

full duplex communication with both data out and data in synchronized with the same clock

signal (which is provided by the master device via the SCK pin).

Slave select (NSS) pin management

A hardware or software slave select management configuration can be set using the

Software slave select management (SSM) bit from the SPI_CR2 register.

•

Software NSS management (SSM = 1): with this configuration, slave select

information is driven internally by the Internal slave select (SSI) bit value in the

SPI_CR2 register.The external NSS pin remains free for other application uses.

•

Hardware NSS management (SSM = 0): For devices set as master, this configuration

allows multimaster capability. For devices set as slave, the NSS pin works as a

classical NSS input. The slave is selected when the NSS line is in low level and is not

selected if the NSS line is in high level.

Note:

When the master is communicating with SPI slaves which need to be deselected between

transmissions, the NSS pin must be configured as a GPIO.

8-BIT SHIFT REGISTER

SPI

CLOCK

GENERATOR

8-BIT SHIFT REGISTER

MISO

MOSI

MISO

SCK

SLAVE

MASTER

NSS

VDD

MSBit

LSBit

MSBit

LSBit

Not used if NSS is managed

by software

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