AN4013 datasheet(11/37 Pages) STMICROELECTRONICS

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AN4013

General-purpose timer modes

Example external clock mode2

In this mode, the update event period is calculated as follows:

Update_event = ETR_CLK/((ETR_PSC)*(PSC + 1)*(ARR + 1)*(RCR + 1))

Where ETR_CLK = the external clock frequency connected to ETR pin.

ETR_CLK = 100 kHz

Prescaler = 1

ETR_PSC = 2

Autoreload = 255

Repetition counter = 2

Update_event= 100*103/((2 + 1)* (1+ 1)*((255 + 1)*(2 + 1))

Update_event = 21.7 Hz

Example external clock mode1

In this mode, the update event period is calculated as follows:

Update_event = TIx_CLK/((PSC + 1)*(ARR + 1)*(RCR +1))

Where TIx_CLK = the external clock frequency connected to TI1 pin or TI2 pin.

TIx_CLK = 50 kHz

Prescaler = 1

Auto reload = 255

Repetition counter = 2

Update_event = 50 000/((1+ 1)*((255 + 1)*(2 + 1))

Update_event = 32.55 Hz

Example Internal trigger clock (ITRx) mode1

In this mode, the update event period is calculated as follows:

Update_event = ITRx_CLK/((PSC + 1)*(ARR + 1)*(RCR + 1))

Where ITRx_CLK = the internal trigger frequency mapped to timer trigger input (TRGI)

ITRx_CLK = 8 kHz

Prescaler = 1

Auto reload = 255

Repetition counter = 1

Update_event = 8000/((1+ 1)*((255 + 1)*(1 + 1))

Update_event = 7.8 Hz

Depending on the counter mode, the update event is generated each:



Overflow, if up counting mode is used: the DIR bit is reset in TIMx_CR1 register



Underflow, if down counting mode is used: the DIR bit is set in TIMx_CR1 register



Overflow and underflow, if center aligned mode is used: the CMS bits are different from

zero.

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