UPD70F3003A datasheet(30/44 Pages) NEC

30 / 44 page

µPD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

(9) CSI timing (1/2)

(a) Master mode

(i)

CSI0-CSI2 timing

Parameter

Symbol

Condition

25 MHz Model

33 MHz Model

Unit

MIN.

MAX.

MIN.

MAX.

SCKn cycle

<67>

tCYSK1

Output

160

120

SCKn width, high

<68>

tWSKH1

Output

0.5 tCYSK1 – 20

SCKn width, low

<69>

tWSKL1

Output

0.5 tCYSK1 – 20

SIn setup time (vs. SCKn

↑)

<70>

tSSISK1

SIn hold time (vs. SCKn

↑)

<71>

tHSKSI1

SOn output delay time (vs. SCKn

↓) <72> tDSKSO1

SOn output hold time (vs. SCKn

↑) <73> tHSKSO1

0.5 tCYSK1 – 5

Remark n = 0-2

(ii) CSI3 timing

Parameter

Symbol

Condition

25 MHz Model

33 MHz Model

Unit

MIN.

MAX.

MIN.

MAX.

SCK3 cycle

<67>

tCYSK3

Output

500

SCK3 width, high

<68>

tWSKH3

Output

0.5 tCYSK3 – 70

SCK3 width, low

<69>

tWSKL3

Output

0.5 tCYSK3 – 70

SI3 setup time (vs. SCK3

↑)

<70>

tSSISK3

100

SI3 hold time (vs. SCK3

↑)

<71>

tHSKSI3

SO3 output delay time (vs. SCK3

↓) <72> tDSKSO3

RL = 1.5 K

Ω

150

CL = 50 pF

SO3 output hold time (vs. SCK3

↑) <73> tHSKSO3

0.5 tCYSK3 – 5

Remark RL and CL are the load resistance and load capacitance respectively of the SCK3 and SO3 output

lines.

(b) Slave mode

(i)

CSI0-CSI2 timing

Parameter

Symbol

Condition

25 MHz Model

33 MHz Model

Unit

MIN.

MAX.

MIN.

MAX.

SCKn cycle

<67>

tCYSK2

Input

160

120

SCKn width, high

<68>

tWSKH2

Input

SCKn width, low

<69>

tWSKL2

Input

SIn setup time (vs. SCKn

↑)

<70>

tSSISK2

SIn hold time (vs. SCKn

↑)

<71>

tHSKSI2

SOn output delay time (vs. SCKn

↓) <72> tDSKSO2

SOn output hold time (vs. SCKn

↑) <73> tHSKSO2

tWSKH2

Remark n = 0-2

RL = 1.5

Ω

CL = 50

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