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AN2641 датащи(PDF) 18 Page - STMicroelectronics |
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AN2641 датащи(HTML) 18 Page - STMicroelectronics |
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18 / 37 page ![]() CLCD interrupts AN2641 18/37 Doc ID 14027 Rev 1 1. Interrupt clear register is a write-only register. Writing logic 1 to the relevant bit clears the corresponding interrupt. This register is mainly used by the interrupt service routine to clear the interrupt, once it is handled. 2. Raw interrupt status register is a read-only register. On a read it returns five bits that can generate interrupts when set. This register can be used to check whether an interrupt occurred. 3. Interrupt mask set/clear register is used to enable the corresponding raw interrupt in the 'Raw Interrupt Status register' (bit values) to be passed to the 'Masked Interrupt Status register'. This read/write register can disable or enable an interrupt. 4. Masked interrupt status register is a read-only register. It is a bit-by-bit logical AND of the 'Interrupt Mask Set/Clear register' and the 'Raw Interrupt Status register'. Interrupt lines correspond to each interrupt. This register can be used to check whether an interrupt is masked. |
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