AN2641 datasheet(17/37 Pages) STMICROELECTRONICS

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AN2641

CLCD interrupts

Doc ID 14027 Rev 1

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CLCD interrupts

The CLCD interrupt is connected the vectored interrupt controller (VIC) as follows:

●

SPEAR600: IRQ45 (CLCD_INTR)

●

SPEAr300: IRQ30 (generic Interrupt #3 from RAS)

5.1

Interrupt causes

There are 4 kinds of event that can cause an CLCD interrupt:

DMA FIFO underflow:

The FIFO underflow interrupt is asserted when data is requested from an empty DMA

FIFO. Note that the size of the DMA FIFO is 32 words.

Setting Watermark Level bit as 1 will cause this interrupt when DMA FIFO has eight or

more empty locations. Setting Watermark Level bit as 0 will cause this interrupt when

DMA FIFO has four or more empty locations.

The interrupt requests the display data from memory, to fill the FIFO to above the

programmed watermark.

Base address update:

The LCD base address update interrupt is asserted when the 'LCD panel frame buffer

base' values are transferred to the 'Current LCD panel frame buffer base'

incrementors. This signals to the system that it is safe to update the 'LCD panel frame

buffer base' registers with new frame base addresses if required.

This interrupt is mainly used to reprogram the base address when generating double-

buffered video.

Vertical compare:

The vertical compare interrupt is asserted when one of four vertical display regions, is

reached. By setting the following values in the LCD V-comp bit in the Control Register

the interrupt can be generated at the:

00 = Start of vertical synchronization

01 = Start of back porch

10 = Start of active video

11 = Start of front porch

Bus Error:

The master bus error interrupt is asserted when an ERROR response is received by

the master interface during a transaction with a slave. When this error is encountered,

the master interface enters an error state and remains in this state until clearance of the

error has been signaled to it (possibly by the interrupt service routine).

●

A single combined interrupt is asserted if any of the above four interrupt lines is

asserted and each interrupt event is handled respectively by the interrupt service

routine.

5.2

Interrupt related registers

There are four registers which are used for handling Interrupts:

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