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AN2836 датащи(PDF) 46 Page - STMicroelectronics |
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AN2836 датащи(HTML) 46 Page - STMicroelectronics |
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46 / 57 page ![]() Demonstration boards AN2836 46/57 Doc ID 15084 Rev 1 The PC software also provides a power dissipation and thermal analysis section, intended to help give a fast evaluation of the device, package and dissipating copper area required by the user’s application, and to be a good starting point for designing an application (from the power dissipation and thermal point of view). Running the demonstration board in standalone mode, instead, R15 and R18 set the reference voltage separately for the two bridges, while R8, C8 and R17, C9 are low-pass filters which provide an external reference voltage by a PWM output of a µC (see also the microstepping section in the AN2839). Using external VREF inputs, R5, R15, R16, R18 should be disconnected, unless the practiSPIN ST7 demonstration board is used. This board, in fact, is provided with an offset cancellation circuitry trimmable through a potentiometer (see PractiSPINTM documentation). R6, C10 and R7, C11 are used to set the off-time of the two channels of the IC. Closing JP2 and JP3 is recommended for safe overcurrent protection. The 5 V voltage for logic inputs and for references (VrefA and VrefB) is obtained from R2 and D3. Depending on the supply voltage, the value of resistor R2 should be changed in order to ensure a correct biasing of D3. The jumper JP1 allows choosing the 5 V voltage from the internal Zener diode network or pin 11 of CN5 (for example an external µC board can provide 5 V to the demonstration board). Also a CN2 connector can be used to provide an external 5 V voltage to the board (in that case R2, D3 should be disconnected). CN2, or pin 1 of CN5, can also be used to provide a 5V voltage to external circuits (as, for example, the PractiSPINTM ST7 board). In this case the current that can be drawn form the board depends on the supply voltage and on the value of R2. Figure 51 to Figure 53 show the placement of the components and the two-layer layout of the L6227PD demonstration board. A large GND area has been used, to guarantee minimal noise and good power dissipation for the device. Figure 49. EVAL6227PD board |
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