AN2335 datasheet(37/40 Pages) STMICROELECTRONICS

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AN2335

Application Information

37/40

9.7

Output data rate selection and reading timing

The output data rate is user selectable through DR bit stored in CTRL_REG1 (20h) register.

At power-on-reset DR is reset to 0 thus providing a default output data rate set to 100 Hz.

The selectable output data rate are given in table below:

The output data rate precision is related to internal oscillator or to external clock precision

and an error of +/- 10% should be taken in account.

The output data rate precision is related to internal oscillator or to external clock precision

and an error of +/- 10% should be taken in account.

A minimum reading period 150

μs shorter than the output data rate period is defined not to

loose any data produced. During this time period the reading of the data must be performed

and DataReady signal can be used as a trigger to begin the reading sequence. At the end of

the complete sequence DataReady signal goes down and the following rise edge advise

that new data are available. If this minimum reading frequency is not observed it is possible

to loose some data and the DataReady signal have no more the meaning of a trigger signal.

The status register can be used to infer whether an overrun condition has happened.

Figure 15.

Reading Timing

Table 6.

Output Data Rate

Output data rate

100 Hz

400 Hz

Table 7.

Timing Value to Avoid Loosing the Data

Time

Description

Min

Typ

Max

Data rate

2.5 ms

10 ms

Reading period

T0-T2

New data generation

150

μs

DataReady

New data available

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