7

Diagnostic Read Operation

When CS goes from high to low (while CLK is high), data

from the diagnostic register is jammed into the serial shift

register, At the same time, the TXD pin exits three-state and

outputs the FSB bit which indicates whether any of the fault

bits in the shift register are set. With the first negative transi-

tion of CLK, the diagnostic register is cleared. Data from the

shift register is shifted to TXD on each low to high transition

of the CLK pulse. The Diagnostic Fault Bits as shown in

Figure 1 are described as follows:

FSB Bit - Indicates that one or more of the bits in the

diagnostic register are set.

TMP Bit - Indicates that the chip temperature has exceeded

occurs; the condition is indicated by the setting of the TMP

bit. Sensors for the TMP bit are located near the power

drivers and are ORed to provide a single bit for the chip.

SCx Bits - Indicate a short-circuit to battery or over current

on the corresponding output. The corresponding output

driver has been latched off. It will remain off until the input is

toggled off and then on.

OLx Bits - Indicate that no load (or a high resistance load) is

connected to the corresponding output. The open load bit is

SGx Bits - Indicate that the voltage on the corresponding

The final 8 bits (most significant bits) of the diagnostic word

indicate the states of the open load and short-to-ground

comparators when the CS pin went from high to low. As

such, an external microprocessor can monitor the status of

the OL and SG comparators directly to cross-check the

action of the filtered fault bits, OL1 to OL4 and SG1 to SG4

(See Figure 1). The action of the filters is to suppress switch-

ing anomalies that may be read as false data. To avoid

potential confusion in normal operation, reading the direct

comparator output bits is not necessary or recommended.

Diagnostic Write Operation

When the R/W pin is in the low state it is possible to write six

bits to the Write/Store register to influence the IC mode of

operation. The write operation is illustrated in Figure 3. The

FSB (First Significant Bit) is present when CS pin goes from

high to low while the CLK pin is high and the R/W pin is in

the high (read) state. The FSB is the error flag and is the

same FSB bit shown for the Figure 1 read operation. When

FSB is high, a read operation is assumed, until or unless the

R/W goes low. When the R/W pin goes low (write mode),

TXD is ready to receive input data. The first write bit occurs

when CLK goes low.

In the write mode, data is latched in the Write/Store register

when CS goes high. The Write/Store data will be in the

default state after a RST reset or power up reset. The write

operation does not affect the data present in the Diagnostic

Register and a read operation does not affect the data

present in the Write/Store Register.

The programmable bits in the Write/Store register are:

Test Bit - Used to put the IC in test mode (not recom-

mended). This bit should be low for normal operation.

ISC Bit - This bit programs the short circuit level for outputs

3 and 4. When this bit is set high the lower value for the cur-

rent shutdown threshold is set.

the delay times for the open-load detection at each of the four

outputs. A logical high sets the open-load delay time to its

shorter value.

Reading Serial Data on the SPI Interface

When interfacing to an 8-bit SPI system and choosing to

read all 22 bits as shown in Figure 1, note that the FSB (First

Significant Bit) is the first bit present before the first CLK

pulse goes low. This leaves 21 bits of available output data

to be shifted by the CLK.

An FSB high state when CS goes low indicates the presents

of a fault bit in the Diagnostic Register. The FSB bit is nor-

mally used as a flag to initiate a read of all data bits in the

shift register. The FSB output bit should be separately

directed to an interrupt or port that is programmed to initiate

a fault data read sequence.

Since SPI data is read 8 bits at a time, reading 24 bits leaves

3 (dummy) bits that follow after the 21 bits of diagnostic fault

output data. Internally, the shift register has an input low

state which will cause the last 3 bits shifted out to be low.

DIRECT COMPARATOR OUTPUTS

CLK

CS

R/W

TXD

ZZ = HIGH IMPEDANCE

ZZZZ

FSB

TMP

SC1

OL1

SG1

SC2

OL2

SG2

SC3

OL3

SG3

SC4

OL4

SG4

OL4

OL1

OL2

OL3

SG4

SG1

SG2

SG3

ZZ

FIGURE 1. SERIAL INTERFACE READ OPERATION

HIP0082, HIP0084