6

Functional Description

Power Output Stages

The Block Diagram details the equivalent logic control of

each power output driver. Each power output stage has a

separately controlled input with hysteresis and is active low

with a pull-up to maintain an off state when there is no input.

Each output driver has sensors for short circuit, open load

and short-to-ground fault detection. The drive to each output

is also controlled by the POR, Reset and an RS latch that

switches off the output when a short circuit occurs. An inter-

nal zener diode feedback from the drain to gate of the output

driver provides over voltage clamp protection.

For the HIP0082, each power output channel has a low

detection while providing one-tenth of the output load current.

and provides controlled slew rate switching. In addition, the

HIP0084 requires an external zener and resistor network for

OL detection. Refer to the Block Diagram, Specifications and

OL Detection information.

Reset Operation

An active low reset on the RST pin or the writing of a Low to

the Test Bit is required to guarantee normal operation after

power-up. When RST is in the low state all outputs are off

and all registers and counters are reset. When the reset pin

When the RST pin is switched active low, the on-chip reset

circuitry ensures that the output stages are turned off, all

counters and registers are reset, and the programmable

functions are in their default states. The default state for the

Test Bit is a Low. The default state for the short-circuit cur-

rent for outputs 3 and 4 is the higher value for 5A maximum

current operation (ISC Bit Low). The default state for the

open-load delay times for each output is the higher value

between 3ms and 5.2ms (Td_OLx Bits Low).

Low Power Drive Shutdown

As part of the POR function, there is a low voltage power

condition the output stages are held off.

Over Voltage Clamp Operation

A drain-to-gate zener diode on each output driver internally

clamps an over voltage pulse, including the kick pulse gener-

ated when turning off an inductive load. While providing over

voltage protection, it is not part of the diagnostic feedback

via the Diagnostic Register.

Short-Circuit (SC) Protection

If the output current is above the current limit for a time delay

sponding bit in the diagnostic register set. The current level for

shutdown on outputs 3 and 4 is programmable between 2A

and 5A with the ISC bit. After shutdown, the output remains

off until the corresponding input is taken high and again low.

Open-Load (OL) Detection

Load currents are monitored while the outputs are ON. If the

open load current falls below the fault threshold current,

The open load fault bits (OLx) are stored in the diagnostic

register as shown in Figure 1. The output of open-load

detector circuit is input to the Diagnostic Register via the delay

filter and is also connected directly to the R/W Shift Register

for potential monitoring via the serial interface.

For the HIP0082 in an ON state, if a load current falls below

teresis, to a normal mode of operation as defined by the

The HIP0084 OL detection diagnostics differ from the

HIP0082. The HIP0084 does not have an internal pullup

resistor (shown in the Block Diagram of the HIP0082 as

OL and a SG fault condition is required, an external

pulldown resistor from OUTx-to-Ground may be used. For a

distinction between an OL and SG fault condition, an exter-

nal pullup resistor in series with a diode between OUTx and

load current detection threshold of OUTx. While the values

for pullup and pulldown resistors are not critical, they

should not be minimally small. In either case, they should

be typically 10k

Ω or greater.

Output Short-to-Ground (SG) Detection

output is off, a ground short is detected and stored in the

short-to-ground (SG) comparators are also connected

directly to the diagnostic register so that they can be moni-

15mA to 100mA for the HIP0084 and 3mA to 20mA for the

HIP0082.

Serial Interface Operation

Microprocessor communication to the diagnostic/control reg-

isters is via a 4 wire serial interface. Data control is bidirec-

tional, the direction of data transfer being dependent on the

state of the R/W pin (See Figure 2).

HIP0082, HIP0084