ADF4112BCPZ datasheet(12/28 Pages) AD

12 / 28 page

ADF4110/ADF4111/ADF4112/ADF4113

Data Sheet

Rev. F | Page 12 of 28

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 28. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This ensures that there is no loading of the REFIN pin

on power-down.

BUFFER

TO R COUNTER

REFIN

100k



SW2

SW3

SW1

POWER-DOWN

CONTROL

Figure 28. Reference Input Stage

RF INPUT STAGE

The RF input stage is shown in Figure 29. It is followed by a

two-stage limiting amplifier to generate the current mode logic

(CML) clock levels needed for the prescaler.

AVDD

AGND

500



500



1.6V

BIAS

GENERATOR

RFINA

RFINB

Figure 29. RF Input Stage

PRESCALER (P/P + 1)

Along with the A and B counters, the dual-modulus prescaler

(P/P + 1) enables the large division ratio, N, to be realized (N =

BP + A). The dual-modulus prescaler, operating at CML levels,

takes the clock from the RF input stage and divides it down to a

manageable frequency for the CMOS A and B counters. The

prescaler is programmable; it can be set in software to 8/9,

16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core.

A AND B COUNTERS

The A and B CMOS counters combine with the dual-modulus

prescaler to allow a wide ranging division ratio in the PLL

feedback counter. The counters are specified to work when the

prescaler output is 200 MHz or less. Thus, with an RF input

frequency of 2.5 GHz, a prescaler value of 16/17 is valid but a

value of 8/9 is not.

Pulse Swallow Function

The A and B counters, in conjunction with the dual-modulus

prescaler, make it possible to generate output frequencies that

are spaced only by the reference frequency divided by R. The

equation for the VCO frequency is

fVCO

= [(P × B) + A]fREFIN/R

where:

fVCO

= output frequency of external voltage controlled oscillator

(VCO)

= preset modulus of dual-modulus prescaler

= preset divide ratio of binary 13-bit counter(3 to 8191)

= preset divide ratio of binary 6-bit swallow counter (0 to 63)

fREFIN

= output frequency of the external reference frequency

oscillator

= preset divide ratio of binary 14-bit programmable reference

counter (1 to 16383)

R COUNTER

The 14-bit R counter allows the input reference frequency to be

divided down to produce the reference clock to the phase

frequency detector (PFD). Division ratios from 1 to 16,383 are

allowed.

13-BIT B

COUNTER

6-BIT A

COUNTER

PRESCALER

P/P + 1

FROM RF

INPUT STAGE

MODULUS

CONTROL

N = BP + A

LOAD

TO PFD

Figure 30. A and B Counters

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