ADE7166_15 datasheet(120/152 Pages) AD

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Rev. B | Page 120 of 152

PLL

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/

ADE7569 are intended for use with a 32.768 kHz watch crystal.

A PLL locks onto a multiple of this frequency to provide a stable

4.096 MHz clock for the system. The core can operate at this

frequency or at binary submultiples of it to allow power savings

when maximum core performance is not required. The default

core clock is the PLL clock divided by 4, or 1.024 MHz. The ADE

energy measurement clock is derived from the PLL clock and is

maintained at 4.096 MHz/5 MHz, 819.2 kHz across all CD

settings.

The PLL is controlled by the CD bits in the power control SFR

(POWCON, Address 0xC5). To protect erroneous changes to

the POWCON SFR, a key is required to modify the register.

First, the key SFR (KYREG, Address 0xC1) is written with the

key, 0xA7, and then a new value is written to the POWCON SFR.

If the PLL loses lock, the MCU is reset and the PLL_FLT bit (Bit 4)

is set in the peripheral configuration SFR (PERIPH, Address 0xF4).

Set the PLLACK bit in the start ADC measurement SFR

(ADCGO, Address 0xD8) to acknowledge the PLL fault,

clearing the PLL_FLT bit.

PLL REGISTERS

Table 125. Power Control SFR (POWCON, Address 0xC5)

Bit

Mnemonic

Default

Description

Reserved

Reserved.

METER_OFF

Set this bit to 1 to turn off the modulators and energy metering DSP circuitry to reduce power if

metering functions are not needed in PSM0.

Reserved

This bit should be kept at 0 for proper operation.

COREOFF

Set this bit to 1 to shut down the core if in the PSM1 operating mode.

Reserved

Reserved.

[2:0]

010

Controls the core clock frequency (fCORE). fCORE = 4.096 MHz/2CD.

Result (fCORE in MHz)

000

4.096

001

2.048

010

1.024

011

0.512

100

0.256

101

0.128

110

0.064

111

0.032

Writing to the Power Control SFR (POWCON, Address 0xC5)

Note that writing data to the POWCON SFR involves writing 0xA7 into the key SFR (KYREG, Address 0xC1) followed by a write to the

POWCON SFR.

Table 126. Key SFR (KYREG, Address 0xC1)

Bit

Mnemonic

Default

Description

[7:0]

KYREG

Write 0xA7 to the KYREG SFR before writing to the POWCON SFR to unlock it.

Write 0xEA to the KYREG SFR before writing to the INTPR, HTHSEC, SEC, MIN, or HOUR timekeeping SFRs

to unlock them.

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