ADE7166_15 datasheet(117/152 Pages) AD

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Rev. B | Page 117 of

152

Table 116. Timer 0 High Byte SFR (TH0, Address 0x8C)

Bit

Mnemonic

Default

Description

[7:0]

TH0

Timer 0 data high byte.

Table 117. Timer 0 Low Byte SFR (TL0, Address 0x8A)

Bit

Mnemonic

Default

Description

[7:0]

TL0

Timer 0 data low byte.

Table 118. Timer 1 High Byte SFR (TH1, Address 0x8D)

Bit

Mnemonic

Default

Description

[7:0]

TH1

Timer 1 data high byte.

Table 119. Timer 1 Low Byte SFR (TL1, Address 0x8B)

Bit

Mnemonic

Default

Description

[7:0]

TL1

Timer 1 data low byte.

Table 120. Timer 2 High Byte SFR (TH2, Address 0xCD)

Bit

Mnemonic

Default

Description

[7:0]

TH2

Timer 2 data high byte.

Table 121. Timer 2 Low Byte SFR (TL2, Address 0xCC)

Bit

Mnemonic

Default

Description

[7:0]

TL2

Timer 2 data low byte.

Table 122. Timer 2 Reload/Capture High Byte SFR

(RCAP2H, Address 0xCB)

Bit

Mnemonic

Default

Description

[7:0]

TH2

Timer 2 reload/

capture high byte.

Table 123. Timer 2 Reload/Capture Low Byte SFR (RCAP2L,

Address 0xCA)

Bit

Mnemonic

Default

Description

[7:0]

TL2

Timer 2 reload/

capture low byte.

TIMER 0 AND TIMER 1

Timer 0 High/Low and Timer 1 High/Low Data SFRs

Each timer consists of two 8-bit SFRs. They are Timer 0 high

byte (TH0, Address 0x8C), Timer 0 low byte (TL0, Address 0x8A),

Timer 1 high byte (TH1, Address 0x8D), and Timer 1 low byte

(TL1, Address 0x8B). These SFRs can be used as independent

registers or combined into a single 16-bit register, depending on

the timer mode configuration (see Table 116 to Table 119).

Timer/Counter 0 and Timer/Counter 1 Operating Modes

This section describes the operating modes for Timer/Counter 0

and Timer/Counter 1. Unless otherwise noted, these modes of

operation are the same for both Timer 0 and Timer 1.

Mode 0 (13-Bit Timer/Counter)

Mode 0 configures an 8-bit timer/counter. Figure 97 shows

Mode 0 operation. Note that the divide-by-12 prescaler is not

present on the single-cycle core.

CONTROL

TR0

TF0

TL0

(5 BITS)

TH0

(8 BITS)

INTERRUPT

P0.6/T0

GATE

INT0

fCORE

C/T0 = 0

C/T0 = 1

Figure 97. Timer/Counter 0, Mode 0

In this mode, the timer register is configured as a 13-bit register.

As the count rolls over from all 1s to all 0s, it sets the timer

overflow flag, TF0 (Address 0x88[5]). TF0 can then be used to

request an interrupt. The counted input is enabled to the timer

when TR0 = 1 and either Gate0 to 0 or INT0 = 1. Setting Gate0

to 1 allows the timer to be controlled by the external input INT0

to facilitate pulse width measurements. TR0 is a control bit in

the Timer/Counter 0 and Timer/Counter 1 control SFR

(TCON, Address 0x88); the Gate0/Gate1 bits are in

Timer/Counter 0 and Timer/Counter 1 mode SFR (TMOD,

Address 0x89). The 13-bit register consists of all eight bits of

Timer 0 high byte SFR (TH0, Address 0x8C) and the lower five

bits of Timer 0 low byte SFR (TL0, Address 0x8A). The upper

three bits of TL0 SFR are indeterminate and should be ignored.

Setting the run flag (TR0) does not clear the registers.

Mode 1 (16-Bit Timer/Counter)

Mode 1 is the same as Mode 0 except that the Mode 1 timer

CONTROL

TR0

TF0

TL0

(8 BITS)

TH0

(8 BITS)

INTERRUPT

P0.6/T0

GATE

INT

C/T0 = 0

C/T0 = 1

fCORE

Figure 98. Timer/Counter 0, Mode 1

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