ADE7166_15 datasheet(118/152 Pages) AD

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

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Mode 2 (8-Bit Timer/Counter with Autoreload)

Mode 2 configures the timer register as an 8-bit counter (TL0)

with automatic reload as shown in Figure 99. Overflow from TL0

not only sets TF0 but also reloads TL0 with the contents of TH0,

which is preset by software. The reload leaves TH0 unchanged.

CONTROL

TF0

TL0

(8 BITS)

INTERRUPT

RELOAD

TH0

(8 BITS)

TR0

P0.6/T0

GATE

INT0

C/T = 0

C/T = 1

fCORE

Figure 99. Timer/Counter 0, Mode 2

Mode 3 (Two 8-Bit Timer/Counters)

Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in

Mode 3 simply holds its count. The effect is the same as setting

TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two

separate counters. This configuration is shown in Figure 100.

TL0 uses the Timer 0 control bits, C/T, Gate0 (see

TR0 and TF0 (see

), and the

Table 113

Table 114

INT0 pin. TH0 is locked

into a timer function (counting machine cycles) and takes over

the use of TR1 and TF1 from Timer 1. Therefore, TH0 controls the

Timer 1 interrupt. Mode 3 is provided for applications requiring

an extra 8-bit timer or counter.

When Timer 0 is in Mode 3, Timer 1 can be turned on and off

by switching it out of and into its own Mode 3, or it can be used

by the serial interface as a baud rate generator. In fact, Timer 1

can be used in any application not requiring an interrupt from

Timer 1 itself.

CONTROL

CORE

CLK/12

TF0

TL0

(8 BITS)

INTERRUPT

P0.6/T0

GATE

TR0

TF1

TH0

(8 BITS)

INTERRUPT

fCORE/12

TR1

INT

C/T = 0

C/T = 1

fCORE

Figure 100. Timer/Counter 0, Mode 3

TIMER 2

Timer/Counter 2 Data Registers

Timer/Counter 2 also has two pairs of 8-bit data registers

associated with it: Timer 2 high byte SFR (TH2, Address 0xCD),

Timer 2 low byte SFR (TL2, Address 0xCC), Timer 2 reload/

capture high byte SFR (RCAP2H, Address 0xCB), and Timer 2

reload/capture low byte SFR (RCAP2L, Address 0xCA). These

are used both as timer data registers and as timer capture/reload

registers (see Table 120 to Table 123).

Timer/Counter 2 Operating Modes

The following sections describe the operating modes for

Timer/Counter 2. The operating modes are selected by bits in

the Timer/Counter 2 control SFR (T2CON, Address 0xC8), as

shown in Table 115 and Table 124.

Table 124. T2CON Operating Modes

RCLK (or) TCLK

CAP2

TR2

Mode

16-bit autoreload

16-bit capture

Baud rate

Off

16-Bit Autoreload Mode

The 16-bit autoreload mode has two options that are selected by

EXEN2 (Bit 3) in the Timer/Counter 2 control SFR (T2CON,

Address 0xC8). If EXEN2 = 0 when Timer 2 rolls over, it not

only sets TF2 but also causes the Timer 2 SFRs to be reloaded

with the 16-bit value in both the Timer 2 reload/capture high byte

SFR (RCAP2H, Address 0xCB) and Timer 2 reload/capture low

byte SFR (RCAP2L, Address 0xCA) registers, which are preset

by software. If EXEN2 = 1, Timer 2 performs the same events as

when EXEN2 = 0 but adds a 1-to-0 transition at the external

input, T2EX, which triggers the 16-bit reload and sets EXF2.

Autoreload mode is shown in Figure 101.

16-Bit Capture Mode

The 16-bit capture mode has two options that are selected by

EXEN2 (Bit 3) in the Timer/Counter 2 control SFR (T2CON,

Address 0xC8). If EXEN2 = 0, Timer 2 is a 16-bit timer or

counter that, upon overflowing, sets the Timer 2 overflow bit

(TF2, Bit 7). This bit can be used to generate an interrupt. If

EXEN2 = 1, then Timer 2 performs the same events as when

EXEN2 = 0, but it adds a l-to-0 transition on the T2E external

input, causing the current value in the Timer 2 SFRs, TL2

(Address 0xCC) and TH2 (Address 0xCD), to be captured into

the RCAP2L (Address 0xCA) and RCAP2H (Address 0xCB)

SFRs, respectively. In addition, the transition at T2EX causes the

EXF2 bit (Bit 6) in the T2CON SFR (Address 0xC8) to be set,

and EXF2, like TF2, can generate an interrupt. Capture mode is

shown in Figure 102. The baud rate generator mode is selected

by RCLK = 1 and/or TCLK = 1.

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