3-27

TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES

STATE

I

N

SYMBOL

OPERATION

DATA

BUS

MEMORY

ADDRESS

MRD

MWR

N

LINES

NOTES

S1

RESET

0

→ I, N, Q, X, P; 1 → lE

00

XXXX

1

1

0

1

Initialize, Not Programmer

Accessible

0000

→ R

00

XXXX

1

1

0

2

S0

FETCH

MRP

→ l, N; RP + 1 → RP

MRP

RP

0

1

0

3

S1

0

0

lDL

IDLE

MR0

RO

0

1

0

4, Fig. 8

0

1 - F

LDN

MRN

→ D

MRN

RN

0

1

0

Fig. 8

1

0 - F

INC

RN + 1

→ RN

Float

RN

1

1

0

Fig. 6

2

0 - F

DEC

RN - 1

→ RN

Float

RN

1

1

0

Fig. 6

3

0 - F

Short Branch

Taken: MRP

→ RP.0

Not Taken; RP + 1

→ RP

MRP

RP

0

1

0

Fig. 8

4

0 - F

LDA

MRN

→ D; RN + 1 → RN

MRN

RN

0

1

0

Fig. 8

5

0 - F

STR

D

→ MRN

D

RN

1

0

0

Fig. 7

6

0

IRX

RX + 1

→ RX

MRX

RX

0

1

0

Fig. 7

6

1

OUT 1

MRX

→ BUS; RX + 1 → RX

MRX

RX

0

1

1

Fig. 11

2

OUT 2

2

Fig. 11

3

OUT 3

3

Fig. 11

4

OUT 4

4

Fig. 11

5

OUT 5

5

Fig. 11

6

OUT 6

6

Fig. 11

7

OUT 7

7

Fig. 11

9

INP 1

BUS

→ MRX, D

Data from

I/O Device

RX

1

0

1

Fig. 10

A

INP 2

2

Fig. 10

B

INP 3

3

Fig. 10

C

INP 4

4

Fig. 10

D

INP5

5

Fig. 10

E

INP6

6

Fig. 10

F

INP7

7

Fig. 10

7

0

RET

MRX

→ (X, P); RX + 1 → RX;

1

→ lE

MRX

RX

0

1

0

Fig. 8

1

DlS

MRX

→ (X, P); RX + 1 → RX;

0

→ lE

MRX

RX

0

1

0

Fig. 8

2

LDXA

MRX

→ D; RX + 1 → RX

MRX

RX

0

1

0

Fig. 8

3

STXD

D

→ MRX; RX - 1 → RX

D

RX

1

0

0

Fig. 7

4

ADC

MRX + D + DF

→ DF, D

MRX

RX

0

1

0

Fig. 8

5

SDB

MRX - D - DFN

→ DF, D

MRX

RX

0

1

0

Fig. 8

6

SHRC

LSB(D)

→ DF; DF → MSB(D)

Float

RX

1

1

0

Fig. 6

7

SMB

D - MRX - DFN

→ DF, D

MRX

RX

0

1

0

Fig. 8

8

SAV

T

→ MRX

T

RX

1

0

0

Fig. 7

CDP1802A, CDP1802AC, CDP1802BC