CDP1802BCEX datasheet(18/27 Pages) INTERSIL

18 / 27 page

3-20

MA0 to MA7 (8 Memory Address Lines)

In each cycle, the higher-order byte of a 16-bit CPU memory

address appears on the memory address lines MA0-7 ﬁrst.

Those bits required by the memory system can be strobed

into external address latches by timing pulse TPA. The low

order byte of the 16-bit address appears on the address lines

after the termination of TPA. Latching of all 8 higher-order

address bits would permit a memory system of 64K bytes.

MWR (Write Pulse)

A negative pulse appearing in a memory-write cycle, after

the address lines have stabilized.

MRD (Read Level)

A low level on MRD indicates a memory read cycle. It can be

used to control three-state outputs from the addressed mem-

ory which may have a common data input and output bus. If a

memory does not have a three-state high-impedance output,

MRD is useful for driving memory/bus separator gates. It is

also used to indicate the direction of data transfer during an

I/O instruction. For additional information see Table 1.

Single bit output from the CPU which can be set or reset

under program control. During SEQ or REQ instruction exe-

cution, Q is set or reset between the trailing edge of TPA and

the leading edge of TPB.

CLOCK

Input for externally generated single-phase clock. The clock is

counted down internally to 8 clock pulses per machine cycle.

XTAL

Connection to be used with clock input terminal, for an exter-

nal crystal, if the on-chip oscillator is utilized. The crystal is

connected between terminals 1 and 39 (CLOCK and XTAL)

in parallel with a resistance (10M

Ω typ). Frequency trimming

capacitors may be required at terminals 1 and 39. For addi-

tional information, see Application Note AN6565.

WAIT, CLEAR (2 Control Lines)

Provide four control modes as listed in the following truth table:

VDD, VSS, VCC (Power Levels)

The internal voltage supply VDD is isolated from the

Input/Output voltage supply VCC so that the processor may

operate at maximum speed while interfacing with peripheral

devices operating at lower voltage. VCC must be less than or

equal to VDD. All outputs swing from VSS to VCC. The recom-

mended input voltage swing is VSS to VCC.

Architecture

The CPU block diagram is shown in Figure 2. The principal

feature of this system is a register array (R) consisting of six-

teen 16-bit scratchpad registers. Individual registers in the

array (R) are designated (selected) by a 4-bit binary code

from one of the 4-bit registers labeled N, P and X. The con-

tents of any register can be directed to any one of the follow-

ing three paths:

1. The external memory (multiplexed, higher-order byte ﬁrst,

on to 8 memory address lines).

2. The D register (either of the two bytes can be gated to D).

3. The increment/decrement circuit where it is increased or

decreased by one and stored back in the selected 16-bit

The three paths, depending on the nature of the instruction,

may operate independently or in various combinations in the

same machine cycle.

With two exceptions, CPU instruction consists of two 8-

clock-pulse machine cycles. The ﬁrst cycle is the fetch cycle,

and the second - and third if necessary - are execute cycles.

During the fetch cycle the four bits in the P designator select

one of the 16 registers R(P) as the current program counter.

The selected register R(P) contains the address of the mem-

ory location from which the instruction is to be fetched.

When the instruction is read out from the memory, the higher

order 4 bits of the instruction byte are loaded into the register

and the lower order 4 bits into the N register. The content of

the program counter is automatically incremented by one so

that R(P) is now “pointing” to the next byte in the memory.

The X designator selects one of the 16 registers R(X) to

“point” to the memory for an operand (or data) in certain ALU

or I/O operations.

The N designator can perform the following ﬁve functions

depending on the type of instruction fetched:

1. Designate one of the 16 registers in R to be acted upon

during register operations.

2. Indicate to the I/O devices a command code or device

selection code for peripherals.

3. Indicate the speciﬁc operation to be executed during the

ALU instructions, types of test to be performed during the

Branch instruction, or the speciﬁc operation required in a

class of miscellaneous instructions (70 - 73 and 78 - 7B).

4. Indicate the value to be loaded into P to designate a new

5. Indicate the value to be loaded into X to designate a new

The registers in R can be assigned by a programmer in three

different ways: as program counters, as data pointers, or as

scratchpad locations (data registers) to hold two bytes of data.

Program Counters

Any register can be the main program counter; the address

of the selected register is held in the P designator. Other reg-

CLEAR

WAIT

MODE

LOAD

RESET

PAUSE

RUN

CDP1802A, CDP1802AC, CDP1802BC

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