3-19

Signal Descriptions

Bus 0 to Bus 7 (Data Bus)

8-bit bidirectional DATA BUS lines. These lines are used for

transferring data between the memory, the microprocessor,

and I/O devices.

N0 to N2 (I/O Control Lines)

Activated by an I/O instruction to signal the I/O control logic of

a data transfer between memory and I/O interface. These

lines can be used to issue command codes or device selec-

tion codes to the I/O devices (independently or combined with

the memory byte on the data bus when an I/O instruction is

being executed). The N bits are low at all times except when

an I/O instruction is being executed. During this time their

state is the same as the corresponding bits in the N register.

The direction of data flow is defined in the I/O instruction by bit

N3 (internally) and is indicated by the level of the MRD signal.

EF1 to EF4 (4 Flags)

These inputs enable the I/O controllers to transfer status

information to the processor. The levels can be tested by the

conditional branch instructions. They can be used in con-

junction with the INTERRUPT request line to establish inter-

rupt priorities. These flags can also be used by I/O devices

to “call the attention” of the processor, in which case the pro-

gram must routinely test the status of these flag(s). The

flag(s) are sampled at the beginning of every S1 cycle.

INTERRUPT, DMA-lN, DMA-OUT (3 I/O Requests)

These inputs are sampled by the CPU during the interval

between the leading edge of TPB and the leading edge of

TPA.

Interrupt Action - X and P are stored in T after executing

current instruction; designator X is set to 2; designator P is

set to 1; interrupt enable is reset to 0 (inhibit); and instruction

execution is resumed. The interrupt action requires one

machine cycle (S3).

DMA Action - Finish executing current instruction; R(0)

points to memory area for data transfer; data is loaded into

or read out of memory; and increment R(0).

NOTE: In the event of concurrent DMA and Interrupt requests,

DMA-lN has priority followed by DMA-OUT and then Interrupt.

SC0, SC1, (2 State Code Lines)

These outputs indicate that the CPU is: 1) fetching an

instruction, or 2) executing an instruction, or 3) processing a

DMA request, or 4) acknowledging an interrupt request. The

levels of state code are tabulated below. All states are valid

TPA, TPB (2 Timing Pulses)

Positive pulses that occur once in each machine cycle (TPB

follows TPA). They are used by I/O controllers to interpret

codes and to time interaction with the data bus. The trailing

edge of TPA is used by the memory system to latch the

higher-order byte of the 16-bit memory address. TPA is sup-

pressed in IDLE when the CPU is in the load mode.

NOTE: IDLE = “00” AT M(0000), BRANCH = “3707” AT M(8107), CL = 50pF

FIGURE 23. TYPICAL POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY FOR BRANCH INSTRUCTION AND IDLE

INSTRUCTION FOR ALL TYPES

0.01

0.1

1

10

0.1

1

10

100

1000

BRANCH

IDLE

STATE TYPE

STATE CODE LINES

SC1

SC0

S0 (Fetch)

L

L

S1 (Execute)

L

H

S2 (DMA)

H

L

S3 (Interrupt)

H

H

CDP1802A, CDP1802AC, CDP1802BC