IMC010FLSA datasheet(3/39 Pages) INTEL

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SERIES 2 FLASH MEMORY CARDS

Table 2 Series 2 Flash Memory Card Pin Descriptions

Symbol

Type

Name and Function

A0–A25

ADDRESS INPUTS

A0 through A25 are address bus lines which enable direct

addressing of 64 megabytes of memory on a card A0 is not used in word

access mode A24 is the most significant address bit Note A25 is a no-connect

but should be provided on host side

DQ0–DQ15

DATA INPUTOUTPUT

DQ0 through DQ15 constitute the bidirectional data

bus DQ15 is the most significant bit

CE1

CE2

CARD ENABLE 1 2

CE1

enables even bytes CE2

enables odd bytes

Multiplexing A0 CE1

and CE2

allows 8-bit hosts to access all data on DQ0

through DQ7 (See Table 3 for a more detailed description)

OUTPUT ENABLE

Active low signal gating read data from the memory card

WRITE ENABLE

Active low signal gating write data to the memory card

RDYBSY

READYBUSY OUTPUT

Indicates status of internally timed erase or write

activities A high output indicates the memory card is ready to accept

accesses A low output indicates that a device(s) in the memory card is(are)

busy with internally timed activities See text for an alternate function (READY-

BUSY MODE REGISTER)

CD1

CD2

CARD DETECT 1 2

These signals provide for correct card insertion detection

They are positioned at opposite ends of the card to detect proper alignment

The signals are connected to ground internally on the memory card and will be

forced low whenever a card is placed in the socket The host socket interface

circuitry shall supply 10K or larger pull-up resistors on these signal pins

WRITE PROTECT

Write Protect reflects the status of the Write-Protect switch

on the memory card WP set high e write protected providing internal

hardware write lockout to the flash array

VPP1 VPP2

WRITEERASE POWER SUPPLY

(12V nominal) for erasing memory array

blocks or writing data in the array They must be 12V to perform an erasewrite

operation

VCC

CARD POWER SUPPLY

(5V nominal) for all internal circuitry

GND

GROUND

for all internal circuitry

REG

provides access to Series 2 Flash Memory Card registers

and Card Information Structure in the Attribute Memory Plane

RST

RESET

from system active high Places card in Power-On Default State

RESET pulse width must be t 200 ns

WAIT

WAIT (Extend Bus Cycle)

is used by Intel’s IO cards and is driven high

BVD1 BVD2

BATTERY VOLTAGE DETECT

Upon completion of the power on reset cycle

these signals are driven high to maintain SRAM-card compatibility

RFU

RESERVED FOR FUTURE USE

NO INTERNAL CONNECTION

Pin may be driven or left floating

VS1 VS2

VOLTAGE SENSE

Notifies the host Socket of the card’s VCC requirements

VS1 and VS2 are both open indicating a 5V VCC card

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