| поискавой системы для электроныых деталей |
|
IMC010FLSA датащи(PDF) 13 Page - Intel Corporation |
|
|
|||||||||||||||||||||||||||||
IMC010FLSA датащи(HTML) 13 Page - Intel Corporation |
|
13 / 39 page ![]() SERIES 2 FLASH MEMORY CARDS WRITE PROTECTION REGISTER (ReadWrite Register) ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 4104H RESERVED FOR FUTURE USE CMWP CISWP 1 e WRITE PROTECT Figure 8 WRITE PROTECTION REGISTER (Intel) Eliminates Accidental Data Corruption SLEEP CONTROL REGISTER (INTEL) Unlike the GLOBAL RESET-POWERDOWN REGIS- TER which simultaneously resets and places all flash memory devices into a Deep-Sleep mode the SLEEP CONTROL REGISTER (Attribute Memory Plane Address 4118H – 411AH Figure 9) allows se- lective power-down control of individual device pairs Writinga1toa specific bit of the SLEEP CONTROL REGISTER places the corresponding device pair into the ‘‘Deep-Sleep’’ mode Devices in Deep-Sleep are not accessible On cards with fewer than 20 Megabytes (10 device pairs) writing a one to an absent device pair has no affect and reads back as zero This register contains all zeroes (ie not in Deep- Sleep mode) when the card powers up or after a hard or soft reset Furthermore the Global Reset- PowerDown Register has no affect on the contents of this register Therefore any bit settings of the Sleep Control Register will remain unchanged after returning from a global reset and power down (writ- ing a zero to the RP bit of the Global Reset-Power- Down Register) READY-BUSY STATUS REGISTER (INTEL) The bits in the Read-only READY-BUSY Status Register (Attribute Memory Plane Address 4130H- 4134H Figure 10) reflect the status (READYe1 BUSYe0) of each device’s RYBY output A busy condition indicates that a device is currently pro- cessing a data-write or block-erase operation These bits are logically ‘‘AND-ed’’ to form the ReadyBusy output (RDYBSY pin 16) of the PCMCIA interface On memory cards with fewer than 20 devices unused Device RYBY Status Register bits appear as ready SLEEP CONTROL REGISTER (ReadWrite Register) ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 411AH RESERVED DEVICES DEVICES 1819 1617 4118H DEVICES DEVICES DEVICES DEVICES DEVICES DEVICES DEVICES DEVICES 1415 1213 1011 89 67 45 23 01 1 e SELECTED DEVICE PAIR IN POWER-DOWN MODE AND RESET Figure 9 SLEEP CONTROL REGISTER (Intel) Allows Specific Devices to be Reset and Put into Power-Down Mode 13 |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |