19

80960SA

Figure 12. Processor Clock Pulse (CLK2)

Figure 13. RESET Signal Timing

LOW LEVEL (MAX) 0.8V

90%

10%

1.5 V

CLK2

CLK

RESET

OUTPUTS

A

B

C

D

A

B

C

INT0, INT1,

INT3, LOCK

INITIALIZATION PARAMETERS

NOTE: Initialization parameters must be set up at least four CLK2 periods before the first CLK2 “A” edge.