80960SA datasheet(12/39 Pages) INTEL

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80960SA

Table 3. 80960SA Pin Description: Bus Signals (Sheet 1 of 2)

NAME

TYPE

DESCRIPTION

CLK2

SYSTEM CLOCK provides the fundamental timing for 80960SA systems. It is

divided by two inside the 80960SA to generate the internal processor clock.

A31:16

T.S.

ADDRESS BUS carries the upper 16 bits of the 32-bit physical address to memory.

It is valid throughout the burst cycle; no latch is required.

AD15:1, D0

I/O

T.S.

ADDRESS/DATA BUS carries the low order 32-bit addresses and 16-bit data to

and from memory. AD15:4 must be latched since the cycle following the address

cycle carries data on the bus.

A3:1

T.S.

ADDRESS BUS carries the word addresses of the 32-bit address to memory.

These three bits are incremented during a burst access indicating the next word

address of the burst access. Note that A3:1 are duplicated with AD3:1 during the

address cycle.

ALE

T.S.

ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is

asserted during a Ta cycle and deasserted before the beginning of the Td state. It is

active HIGH and floats to a high impedance state during a hold cycle (Th).

T.S.

ADDRESS STATUS indicates an address state. AS is asserted every Ta state and

deasserted during the following Td state. AS is driven HIGH during reset.

W/R

T.S.

WRITE/READ specifies, during a Ta cycle, whether the operation is a write or read.

It is latched on-chip and remains valid during Td cycles.

DEN

T.S.

DATA ENABLE is asserted during Td cycles and indicates transfer of data on the

AD lines. The AD lines should not be driven by an external source unless DEN is

asserted. When DEN is asserted, outputs from the previous cycle are guaranteed

to be three-stated. In addition, DEN deasserted indicates inputs have been

captured; therefore input hold times can be disregarded. DEN is driven HIGH

during reset.

DT/R

T.S.

DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from

the bus. It is low during Ta and Td cycles for a read or interrupt acknowledgment; it

is high during Ta and Td cycles for a write. DT/R never changes state when DEN is

asserted. DT/R is driven HIGH during reset.

READY

READY indicates that data on AD lines can be sampled or removed. If READY is

not asserted during a Td cycle, the Td cycle is extended to the next cycle by

inserting a wait state (Tw).

I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state

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