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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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80960SA датащи(PDF) 19 Page - Intel Corporation |
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80960SA датащи(HTML) 19 Page - Intel Corporation |
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19 / 39 page  15 80960SA 2.8 AC Specifications This section describes the AC specifications for the 80960SA pins. All input and output timings are specified relative to the 1.5V level of the rising edge of CLK2 and refer to the time at which the signal crosses 1.5V (for output delay and input setup). All AC testing should be done with input voltages of 0.4V and 2.4V, except for the clock (CLK2) which should be tested with input voltages of 0.45V and 0.7 x VCC. See Figure 11 and Tables 6, 7 and 8 for timing relationships for the 80960SA signals. Figure 11. Drive Levels and Timing Relationships for 80960SA Signals A B C D A B C 1.5V 1.5V 1.5V 1.5V T6 1.5V 1.5V T7 1.5V 1.5V VALID OUTPUT T6 T8 T8 T13 T14 1.5V 1.5V VALID OUTPUT T9 2.0V 2.0V 2.0V 2.0V 0.8V 0.8V 0.8V 0.8V EDGE CLK2 OUTPUTS: AD15:1, A3:1, D0, W/R, DEN, BLAST, HLDA, LOCK, INTA ALE DT/R INPUTS: AD15:1, D0, INT2, INT3 HOLD LOCK READY T9 T10 T11 T12 T11 A 31:16, BE1:0, INT0, INT1, AS T6AS T6AS VALID INPUT |
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