ICS9250-32

Third party brands and names are the property of their respective owners.

Integrated

Circuit

Systems, Inc.

Block Diagram

9250-32 Rev B 9/7/00

Recommended Application:

Timna Style Chipset

Output Features:

•

3 - CPUs @ 2.5V

•

8 - PCI @ 3.3V

•

2 - IOAPIC @ 2.5V

•

1 - MREF @ 2.5V, DRCG memory reference clock

•

9 - SDRAM @ 3.3V including one free running

•

1 - 2V48M @ 2.5V fixed (DOT)

•

1 - 3V48M @ 3.3V fixed (USB)

•

2 - REF @ 3.3V, 14.318MHz.

Features:

•

Support power management: CPU, PCI, SDRAM stop

from I

•

Spread spectrum for EMI control (0 to -0.5%)

•

Uses external 14.318MHz crystal

Key Specifications:

•

•

•

•

•

•

CPU - CPU: < 175ps

•

SDRAM - SDRAM < 250ps

•

PCI - PCI: < 500ps

•

IOAPIC - IOAPIC: < 250ps

•

BUFFER_IN to SDRAM prop delay: 5.5 to 7.5ns

Functionality

Pin Configuration

56-Pin 300mil SSOP

* These inputs have a 50K pull up to VDD.

Frequency Generator & Integrated Buffers for PII/III™

2V48M

3V48M

VDD48

GND48

X1

X2

GND

*(CPU2_EN#)REF0

REF1

VDD

PCICLK0

PCICLK1

GNDPCI

VDDPCI

PCICLK2

PCICLK3

PCICLK4

PCICLK5

VDDPCI

GNDPCI

PCICLK6

PCICLK7

SCLK

VDDA

GNDA

SDATA

BUF_IN

*FS0

VDDLIOAPIC

IOAPIC0

IOAPIC1

GNDLIOAPIC

VDDLCPU

CPUCLK0

CPUCLK1

VDDLCPU

GNDLCPU

CPUCLK2

MREF66

VDD

SDRAM_F

SDRAM0

VDDSDR

GNDSDR

SDRAM1

SDRAM2

SDRAM3

GNDSDR

VDDSDR

SDRAM4

SDRAM5

VDDSDR

GNDSDR

SDRAM6

SDRAM7

FS1*

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

PLL2

PLL1

Spread

Spectrum

3V48M

2V48M

CPUCLK (2:0)

SDRAM (7:0)

IOAPIC (1:0)

PCICLK (7:0)

8

8

3

2

2

SDRAM_F

MREF66

X1

X2

XTAL

OSC

CPU

DIVDER

SDRAM

DIVDER

IOAPIC

DIVDER

PCI

DIVDER

3V66

DIVDER

REF (1:0)

CPU_EN#

BUF_IN

SDATA

SCLK

FS (1:0)

Control

Logic

Config.

Reg.

1

S

F0

S

F

d

e

h

c

t

a

L

p

u

r

e

w

o

P

#

N

E

_

2

U

P

C

/

1

F

E

R

0

U

P

C

,

1

U

P

C

F

E

R

M

2

U

P

C

11

1

z

H

M

6

6e

t

a

t

s

i

r

T

11

0

z

H

M

6

6z

H

M

6

6

10

X

2

/

K

L

C

T2

/

K

L

C

T

01

X

d

e

v

r

e

s

e

Rd

e

v

r

e

s

e

R

00

X

e

t

a

t

s

i

r

Te

t

a

t

s

i

r

T

Power Groups

VDD = REF, X1, X2

VDDPCI = PCICLK

VDDSDR = SDRAM

VDD48 = 3V48M

VDDLCPU = CPU

VDDLIOAPIC = IOAPIC, 2V48M

VDDA = PLL Core

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

information being relied upon by the customer is current and accurate.