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ICS9250-32 датащи(PDF) 8 Page - Integrated Circuit Systems

номер детали ICS9250-32
подробное описание детали  Frequency Generator & Integrated Buffers for PII/III?
PDF  11 Pages
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производитель  ICST [Integrated Circuit Systems]
домашняя страница  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS9250-32 датащи(HTML) 8 Page - Integrated Circuit Systems

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ICS9250-32
Third party brands and names are the property of their respective owners.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance
1
RDSP2A
VO = VDD*(0.5)
8.5
10.1
24
Ω
Output Impedance
1
RDSN2A
VO = VDD*(0.5)
8.5
12
24
Ω
Output High Voltage
VOH2A
IOH = -1 mA
2.4
3.3
V
Output Low Voltage
VOL2A
IOL = 1 mA
0.006
0.4
V
VOH @ MIN = 2.0 V
-100
-54
VOH @ MAX = 3.135 V
-46
-13
VOL @ MIN = 1.0 V
53
90
VOL @ MAX = 0.4 V
40
54
Rise Time
1
tr2A
VOL = 0.4 V, VOH = 2.4 V
0.4
1
1.6
ns
Fall Time
1
tf2A
VOH = 2.4 V, VOL = 0.4 V
0.4
0.8
1.6
ns
Duty Cycle
1
dt2A
VT = 1.5 V
45
51
55
%
Skew (ouput to output)
1
tsk2A
VT = 1.5 V
212
250
ps
Skew (Buffer In to output)
1
tsk2B
VT = 1.5 V
5.5
6.5
7.5
ns
1Guaranteed by design, not 100% tested in production.
Output Low Current
IOL2A
mA
Output High Current
IOH2A
mA
AC timing of the trise & tfall is controlled by pre-driver circuit which allows lower impedance output to stay in the middle of
transition time target.
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-15 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance
1
RDSP5
VO = VDD*(0.5)
16
24
60
Ω
Output Impedance
1
RDSN5
VO = VDD*(0.5)
16
19.2
60
Ω
Output High Voltage
VOH5
IOH = -1 mA
2.4
3.3
V
Output Low Voltage
VOL5
IOL = 1 mA
0.014
0.4
V
VOH @ MIN = 2.0 V
-65
-27
VOH @ MAX = 3.135 V
-23
-8
VOL @ MIN = 1.0 V
29
65
VOL @ MAX = 0.4 V
21
27
Rise Time
1
tr5
VOL = 0.4 V, VOH = 2.4 V
1.4
4
ns
Fall Time
1
tf5
VOH = 2.4 V, VOL = 0.4 V
1.4
4
ns
Duty Cycle
1
dt5
VT = 1.5 V
45
54
55
%
Jitter, Cycle-to-cycle
1
tjcyc-cyc5
VT = 1.5 V, CPU=66,100,133 MHz
674
1000
ps
1Guaranteed by design, not 100% tested in production.
mA
Output High Current
IOH5
mA
AC timing of the trise & tfall is controlled by pre-driver circuit which allows lower impedance output to stay in the middle of
transition time target.
Output Low Current
IOL5



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