2

ICS9250-32

Third party brands and names are the property of their respective owners.

Functionality

The ICS9250-32 is the single chip clock solution for Desktop designs. It provides all necessary clock signals for such a system.

This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-32 employs a

proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.

General Description

Pin Configuration

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

1

2V48M

OUT

48MHz output clock 2.5V (DOT) clock

2

3V48M

OUT

48MHz output clock 3.3V (USB) clock

3, 10, 14, 19, 24,

33, 36, 42, 45

VDD

PWR

3.3V Power supply for SDRAM output buffers, PCI output buffers,

reference output buffers and 3V48 output

4, 7, 13, 20, 25,

32, 37, 41, 48, 53

GND

PWR

Ground pins

5

X1

IN

Crystal input,nominally 14.318MHz.

6

X2

OUT

Crystal output, nominally 14.318MHz.

CPU2_EN#

IN

Disables CPU2 when pulled high (default)

Enables CPU2 when pulled Low

REF0

OUT

14.318 MHz reference clock.

9

REF1

OUT

14.318 MHz reference clock.

22, 21, 18, 17, 16,

15, 12, 11

PCICLK (7:0)

OUT

PCI clock outputs.

23

SCLK

IN

Clock pin of I

2

C circuitry 5V tolerant

26

SDATA

I/O

Data pin for I

2

C circuitry 5V tolerant

27

BUF_IN

IN

Input to fan out buffer for SDRAM

28

FS0

IN

Frequency select pin.

29

FS1

IN

Frequency select pin.

30, 31, 34, 35, 38,

39, 40, 43

SDRAM (7:0)

OUT

SDRAM clock outputs

44

SDRAM_F

OUT

SDRAM clock output free running not affected by I

2

C

46

MREF66

OUT

DRCG reference memory 2.5V 66MHz

49, 52, 56

VDDL

PWR

Power pins for CPUCLKs, and IOAPIC clocks. 2.5V

47, 50, 51

CPUCLK (2:0)

OUT

2.5V CPU clock outputs.

54, 55

IOAPIC (1:0)

OUT

2.5V IOAPIC clock outputs

8

1

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