NHIXP435AD datasheet(14/24 Pages) INTEL

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4.0 Non-Intel XScale® Technology Errata Descriptions

Intel® IXP43X Product Line of Network Processors

Specification Update

December 2008

Order Number: 316847; Revision: 005US

12.

Ethernet Coprocessors — Address Filtering Logic Ignores the Second

to Last Nibble of the Destination Address

Problem:

The Intel® IXP43X Product Line of Network Processors has an Ethernet coprocessor

configured by the Intel® IXP400 Software. The Ethernet coprocessor logic ignores the

second last nibble of the destination address regardless of the packet type (unicast,

multicast, broadcast), that is, Destination Address: 11 22 33 44 55 x6. The reason it is

the second last is that the address is transmitted on the line with high nibble first and

then the low nibble.

Implication: Some Ethernet frames with wrong destination address can get through the Address

Filter.

Workaround: A software workaround is possible using the ixEthDb filtering capabilities.

Status:

No Fix.

13.

Ethernet MACs Detect Late Collision Earlier Than Ethernet 802.3

Specifications

Problem:

On an improperly designed network, when a collision occurs on the threshold of the

smallest valid Ethernet frame, it is detected as a late collision rather than an early

collision.

Implication: The collided frame will not be retried up to the programmed retry count and will be

dropped.

Workaround: Cable lengths, number of repeaters, and other parameters that affect the network

design must be planned not to operate on the boundary of the Ethernet specifications.

Status:

No Fix.

14.

Read of PCI Controllers BAR 32'h XXFF_FFFC Rd[N] Corrupts

Subsequent Rd[N+1]

Problem:

If specifically reading the ‘last word’ address of a BAR register, read(n), and if that BAR

BAR register), this read(n) will complete correctly, but will cause data corruption in the

subsequent read (n+1).

Implication: Upon the next subsequent external PCI master read Rd[N+1], the PCI controller

returns incorrect read data of Rd[N].

Workaround: Avoid reading the last word of the BAR or avoid reading this one BAR entirely. The

setup could be changed such that the BAR registers are adjacent to each other in

memory space and place the config BAR 4 on top of the final BAR so that no “last word”

address in each memory address BAR0-3 is adjacent to undefined memory space. For

example:

Status:

No Fix.

15.

UART Operating in Non-FIFO Mode Can Falsely Receive Overrun Error

Problem:

If the UART is operating in non-FIFO mode, there is a possibility of falsely receiving an

Overrun Error under certain conditions even though an overrun did not occur.

Implication: An erroneous interrupt to the Intel XScale processor may occur indicating that data was

lost in the UART.

Workaround: Using the UART in FIFO mode or in non-FIFO mode, the data should be rejected and

resent.

BAR4 - config BAR: highest address

BAR3

BAR2

BAR1

BAR0 - lowest address

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