December 2008

Specification Update

11

4.0

1.

HDLC Coprocessor Is Unable to Capture the Alignment Error on a

Specific Frame Pattern

Problem:

Based on ITU-T Q.921, during transmission, a bit stuffing ‘0’ is inserted after five

consecutive ‘1’ bits (including the FCS field) and then removed at the receiving end.

The bit stuffing ensures that the data does not appear as the ‘end of frame’ flag

(01111110). If five ‘1’s are received without a bit stuffing ‘0’, a ‘byte alignment error’

will be issued. The HDLC controller of the IXP43X product line of network processors

will not issue a ‘byte alignment error’ when the following boundary condition occurs:

1. The receiving frame ends with five ‘1’s (FCS) followed by an ‘end of frame’ flag:

“xx011111 01111110”

AND

2. The ‘end of frame’ flag received is byte aligned.

controller from a Q.921 compliant HDLC controller with the same pattern described

above will not generate a ‘byte alignment error’; an FCS error will be issued by the

HDLC controller.

Status:

No Fix.

2.

PCI Accesses to the Queue Manager During Queue and SRAM Mode

Problem:

Under certain data traffic, the PCI controller may generate spurious write transfers and

may return incorrect data on reads while accessing the Queue Manager in SRAM mode.

Additionally, if the Queue Manager is being used in the Queue mode, PCI accesses must

not use memory-mapped registers BAR0-3 as these accesses cause pre-fetches during

reads.

DDRII/DDRI SDRAM memory space while generating PCI accesses to the memory

space of the IXP43X network processors. An external PCI master must use PCI BAR5

while accessing the Queue Manager in Queue mode.

Status:

No Fix.

3.

Ethernet Control Protocol Frames Transmit-Defer Status Bit Error

Problem:

Ethernet control protocol transmit frames of size 64 or less result in the Transmit-Defer

status bit being set regardless of the gap between the frames.

Status:

No Fix.

4.

PCI Doorbell Register Lock-up Condition When Using Two Products

Problem:

It is possible that the PCI bus can get in a locked condition when multiple products

using the IXP4XX product line processors are connected in a system and these systems

are using the PCI doorbell registers of the IXP4XX product line processors. This lockup

occurs only when both the IXP4XX product line processors attempt to access each

other’s PCI doorbell register at a particular instance. This error occurs only on reads of

the of the doorbell register.

doorbell registers, PCI doorbell register reads cannot be implemented.

memory to pass information.

Status:

No Fix.