WM1811A datasheet(97/328 Pages) WOLFSON

97 / 328 page

Production Data

WM1811A

PD, November 2013, Rev 4.1

SAMPLE

RATE (kHz)

SYSCLK RATE (AIFnCLK / fs ratio)

128

192

256

384

512

768

1024

1536



11.025

Note 1



Note 1



Note 1



22.05

Note 1



Note 1



Note 1



44.1

Note 1



Note 1



88.2

Note 1

When DAC_OSR128=0, DAC operation is only supported for the configurations indicated above

Table 51 DAC Clocking - DAC_OSR128 = 0 (Default)

SAMPLE

RATE (kHz)

SYSCLK RATE (AIFnCLK / fs ratio)

128

192

256

384

512

768

1024

1536



11.025



22.05

Note 1



Note 1



Note 1



44.1

Note 1



Note 1



88.2

Note 1

When DAC_OSR128=1, DAC operation is only supported for the configurations indicated above

Table 52 DAC Clocking - DAC_OSR128 = 1

Note 1 - These clocking rates are only supported for ‘simple’ DAC-only playback modes, under the

following conditions:



AIF input is enabled on a single interface (AIF1 or AIF2) only, or is enabled on AIF1 and

AIF2 simultaneously provided AIF1 and AIF2 are synchronised (ie. AIF1CLK_SRC =

AIF2CLK_SRC)



All AIF output paths are disabled



All DSP functions (ReTune™ Mobile Parametric Equaliser, 3D stereo expansion and

Dynamic Range Control) are disabled

The clocking requirements in Table 51 and Table 52 are only applicable to the AIFnCLK that is

selected as the SYSCLK source. Note that both clocks (AIF1CLK and AIF2CLK) must satisfy the

requirements noted in the “Clocking and Sample Rates” section.

The applicable clocks (SYSCLK, and AIF1CLK or AIF2CLK) must be present and enabled when using

the Digital to Analogue Converters (DACs).

Note that the presence of a suitable clock is automatically detected by the WM1811A; if the clock

signal is absent, then any speaker or earpiece output driver(s) associated with the DAC signal paths

will be disabled. (This is applicable to the SPKOUTL, SPKOUTR and HPOUT2 outputs only,

whenever one or more DAC is routed to these output drivers.)

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