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ML7344J датащи(PDF) 66 Page - List of Unclassifed Manufacturers |
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ML7344J датащи(HTML) 66 Page - List of Unclassifed Manufacturers |
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66 / 151 page ![]() FEDL7344C/E/J-04 ML7344C/E/J 66/151 (3) Channel space setting Channel space can be set by [CH_SPACE_H: B1 0x23], [CH_SPACE_L: B1 0x24] registers. Hexadecimal values calculated in the following formula should be set to [CH_SPACE_H: B1 0x23], [CH_SPACE_L: B1 0x24] registers. (MSB->LSB order) When enabling PLL 1/2 division mode by setting PLL_MODE ([PLL_DIV_SET:B1 0x1A(4)])=0b1, calcurated with fref =FMCK1/2 in the following formula. Channel space is from the center frequency of given channel to adjacent channel center frequency. Channel space setting value can be calculated using the following formula: 20 2 _ ⋅ ⎪⎭ ⎪ ⎬ ⎫ ⎪⎩ ⎪ ⎨ ⎧ = ref sp f f SPACE CH (Integer part) Here : _ SPACE CH Channel space setting : sp f Channel space [MHz] : ref f PLL reference frequency (=master clock frequency : FMCK1) [Example] When set channle space to 25kHz (master clock 26MHz), the calculation is as follows. 20 2 26 025 . 0 _ ⋅ ⎭ ⎬ ⎫ ⎩ ⎨ ⎧ = MHz MHz SPACE CH (Integer part) = 1008 (0x03F0) [CH_SPACE_H: B1 0x23] = 0x03 [CH_SPACE_L: B1 0x24] = 0xF0 |
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